EmbDev.net

Forum: FPGA, VHDL & Verilog how to handle this line of Verilog

von Sylvain N. (Company: myself) (mpgguy)

2017-11-21 15:24

Rate this post

•	▲ useful ▼ not useful

I am currently converting some Verilog into VHDL

that goes quite well till now : I don't know how to handle that 
expression'
'
8b'001100111

I checked I really need only 8 bits ... so obviously there's one extra 
bit in this expression ... and the Verilog code was "working"

You have any idea which bit is "forgotten".... the first 0 ... or the 
last 1 ??

Thank you

Report post Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote

Re: how to handle this line of Verilog

von Lothar M. (Company: Titel) (lkmiller) (Moderator)

2017-11-21 15:34

Rate this post

•	▲ useful ▼ not useful

Sylvain N. wrote:
> I checked I really need only 8 bits ... so obviously there's one extra
> bit in this expression ... and the Verilog code was "working"
See there at "integer numbers":
http://www.asic-world.com/verilog/syntax1.html
"... the leftmost bits are truncated."