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Forum: FPGA, VHDL & Verilog how to handle this line of Verilog


Author: Sylvain N/a (Company: myself) (mpgguy)
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I am currently converting some Verilog into VHDL

that goes quite well till now : I don't know how to handle that 
expression'
'
8b'001100111

I checked I really need only 8 bits ... so obviously there's one extra 
bit in this expression ... and the Verilog code was "working"

You have any idea which bit is "forgotten".... the first 0 ... or the 
last 1 ??

Thank you

Author: Lothar Miller (lkmiller) (Moderator)
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Sylvain N. wrote:
> I checked I really need only 8 bits ... so obviously there's one extra
> bit in this expression ... and the Verilog code was "working"
See there at "integer numbers":
http://www.asic-world.com/verilog/syntax1.html
"... the leftmost bits are truncated."

Author: Sylvain N/a (Company: myself) (mpgguy)
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Thank you so much

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