how to handle this line of Verilog

I am currently converting some Verilog into VHDL

that goes quite well till now : I don't know how to handle that 
expression'
'
8b'001100111

I checked I really need only 8 bits ... so obviously there's one extra 
bit in this expression ... and the Verilog code was "working"

You have any idea which bit is "forgotten".... the first 0 ... or the 
last 1 ??

Thank you