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function in VHDL- make binary
von Noa C. (Company: noacohen) (noa_cohen_2000)

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what the function MAKE_BINARY  does in VHDL ?
What its puprose?

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Re: function in VHDL- make binary
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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Noa C. wrote:
> what the function MAKE_BINARY  does in VHDL ?
Simply have a look in the source of the std_logic_arith package:
https://www.csee.umbc.edu/portal/help/VHDL/packages/std_logic_arith_syn.vhd
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    -- synopsys synthesis_off

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    type tbl_type is array (STD_ULOGIC) of STD_ULOGIC;

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    constant tbl_BINARY : tbl_type :=

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  ('X', 'X', '0', '1', 'X', 'X', '0', '1', 'X');

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    -- synopsys synthesis_on

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    function MAKE_BINARY(A : STD_ULOGIC) return STD_ULOGIC is

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  -- synopsys built_in SYN_FEED_THRU

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    begin

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  -- synopsys synthesis_off

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      if (IS_X(A)) then

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    assert false 

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    report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."

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    severity warning;

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          return ('X');

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      end if;

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      return tbl_BINARY(A);

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  -- synopsys synthesis_on

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    end;


> What its puprose?
It takes the input vector and makes a '1' out of a '1' or a 'H", and it 
makes a '0' out of a '0' and a 'L', all the rest will be changed to 'X'.

BTW: I recoomend NOT to use the old Synopsys std_logic_arith libs. Use 
the numeric_std instead. It has all you will need.

  


  




  

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