Noa C. wrote:
> what the function MAKE_BINARY does in VHDL ?
Simply have a look in the source of the std_logic_arith package:
https://www.csee.umbc.edu/portal/help/VHDL/package...
-- synopsys synthesis_off
type tbl_type is array (STD_ULOGIC) of STD_ULOGIC;
constant tbl_BINARY : tbl_type :=
('X', 'X', '0', '1', 'X', 'X', '0', '1', 'X');
-- synopsys synthesis_on
function MAKE_BINARY(A : STD_ULOGIC) return STD_ULOGIC is
-- synopsys built_in SYN_FEED_THRU
begin
-- synopsys synthesis_off
if (IS_X(A)) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
return ('X');
end if;
return tbl_BINARY(A);
-- synopsys synthesis_on
end;
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> What its puprose?
It takes the input vector and makes a '1' out of a '1' or a 'H", and it
makes a '0' out of a '0' and a 'L', all the rest will be changed to 'X'.
BTW: I recoomend NOT to use the old Synopsys std_logic_arith libs. Use
the numeric_std instead. It has all you will need.
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