while I haven't looked at Vivado PCIe cores yet, I did use them
extensively in ISE13.2 in Virtex6. The base core was an AXI streaming
interface. Xilinx provides some basic TLP processing, but multiplex
everything into a common internal local bus. This may or may not be
acceptable for your project.
I have also dealt with Altera PCIe for S5/A10 and they were very similar
to the Xilinx stuff, but using Avalon.
My recommendation is to design a vanilla PCIe TLP packet processing FSM.
If you do this right, you can quickly adapt it to any FPGA vendor you
may need to use it with. I would highly recommend the huge PCIe book
and if you look hard enough, you can find a PDF of it.
https://www.amazon.com/Express-System-Architecture-Mindshare-Inc/dp/0321156307/ref=pd_lpo_sbs_14_t_0?_encoding=UTF8&psc=1&refRID=7XCRRCK4CDEE2NKJPR76
The other important thing is to decide how you want to use PCIe.
specifically, processing TLPs with multiple DWord payloads, or just
simple, single DWord, PIO like accesses. You could break out each BAR
space (target) as well as add bus mastering capability.
I would recommend your vanilla TLP processing FSM interface to the rest
of your design with WishBone, as it supports burst and non-burst
transactions and is very simple, unlike the painful AXI or Avalon of
Xilinx and Altera. Another benefit since you are going to use LAttice,
is that if you use WishBone, you can easily integrate the MICO32 soft
CPU, if needed.