Hello everyone, I have a project implemented in Virtex5 that I have to convert to ECP5. The Project has a PCI Express core connected with different modules. My Approach is first to generate the PCI Express IP core in lattice and just implement a wrapper in therms of the sending and receiving packets without packet description and later on get into more Detail about the packet description when I will be implementing the Rx and Tx engine. My question is will this be the best approach to implement such Project? Any idea and how it can easily be done is welcome. Thanks in advance
Probably not, the interfacing arrangement to the Lattice and Xilinx PCIe Cores has about as much in common as sheep and cows. The common parts, the horns, are the external connections to the PCIe bus. On the application side it is completely different. Xilinx typically wrap you up in an AXI cushion whereas Lattice expect you to actually understand how PCIe packets are built and decoded. Lattice do have a verilog solution for their Versa kits which add a Wishbone wrapper around their core and which I suppose is a good starting point if that is the way you want to go. If you want to stay with AXI you will have to develop this yourself or get somebody to do it for you. Generic VHDL or Verilog for anything apart from the IP-cores in your design should work except maybe that Vivado seems to accept some constructs which are not really legal or more of a mix between the different language versions (VHDL 2008, 2002, 1993 ...) so you may have to fix things here too.
@charles thank you for your answer. As a newbie in VHDL It would really help me if I can get an example of a VHDL Code of AXI. I don't have Vivado Software as you mention and from the different examples I have seen they are using Vivado for AXI. I only have Xilinx ISE and lattice Diamond in my PC. Is there any way you can help me start the development of the AXI in VHDL? The old Project does not use a Wishbone so I will not be using it. Once again Many thanks for your Reply
Hello guys Is there some simple way I can start from the IP core Generation of the PCI express and followed up with different implementation? Or any other way to Approach such project Please guys I really need your help on this project I feel like any idea I have isn't the best one. Many thanks
Vahr wrote: > As a newbie in VHDL It would really > help me if I can get an example of a VHDL Code of AXI. I don't have > Vivado Software as you mention and from the different examples I have > seen they are using Vivado for AXI. I only have Xilinx ISE and lattice > Diamond in my PC. Is there any way you can help me start the development > of the AXI in VHDL? The old Project does not use a Wishbone so I will > not be using it. Sorry, I don't have any AXI adapters for free. But there are a number of AXI solutions on opencores. You might find what you are looking for here or find a design you can use as an example. e.g. http://opencores.org/project,dma_axi
@charles thanks again for the link. Eventhough it's in Verilog. I haven't found one in VHDL seems like I will have to dig deep. Hope to find something helpful soon. In case anyone has another idea how I can solve this Problem can still help me I really need it. Once again thanks for the link. Many thanks
Just my 5 cents: Don't mess with the braindead AXI overhead if you are a newbie. It sounds like you have a simple streaming engine where you only need to implement a packet FIFO around the PCIe engine. Which board do you have and what are you simulating with?
@strubi thanks for your help. You are right about the AXI thought. Xilinx didn't implement the AXI in the virtex-5 it was in the 6 and above version. I won't use it. The different Problem I am having is the difference in data size (16 for lattice and 32 for Virtex) and the Interrupt too (8 in ECP5 and 32 in Virtex)I am really struggling to see how this can be implemented, did anyone have a VHDL Code for the imterrupt implementation (MSI or MSI-X) as they said any of the two will work. A Streaming with a FIFO Sound like a good idea. Do you know how I can implement that? I am using ECP5 Versa Dev Kit and for the Simulation an Active HDL incorporated in lattice Diamond. Many thanks
while I haven't looked at Vivado PCIe cores yet, I did use them extensively in ISE13.2 in Virtex6. The base core was an AXI streaming interface. Xilinx provides some basic TLP processing, but multiplex everything into a common internal local bus. This may or may not be acceptable for your project. I have also dealt with Altera PCIe for S5/A10 and they were very similar to the Xilinx stuff, but using Avalon. My recommendation is to design a vanilla PCIe TLP packet processing FSM. If you do this right, you can quickly adapt it to any FPGA vendor you may need to use it with. I would highly recommend the huge PCIe book and if you look hard enough, you can find a PDF of it. https://www.amazon.com/Express-System-Architecture-Mindshare-Inc/dp/0321156307/ref=pd_lpo_sbs_14_t_0?_encoding=UTF8&psc=1&refRID=7XCRRCK4CDEE2NKJPR76 The other important thing is to decide how you want to use PCIe. specifically, processing TLPs with multiple DWord payloads, or just simple, single DWord, PIO like accesses. You could break out each BAR space (target) as well as add bus mastering capability. I would recommend your vanilla TLP processing FSM interface to the rest of your design with WishBone, as it supports burst and non-burst transactions and is very simple, unlike the painful AXI or Avalon of Xilinx and Altera. Another benefit since you are going to use LAttice, is that if you use WishBone, you can easily integrate the MICO32 soft CPU, if needed.
@Jackie thanks for your help. I have got the PDF of the PCI Express Ebook eventhough the chapter are not finished there. I will get the hardcopy to get a bit more Information. The virtex Project was implemented with a TLP processing with multiple DWord payloads. I would like to do the same in ECP5. Do you have a VHDL example Code of the vanilla TLP processing FSM Interface? Hopefully if I have it I might be able to modify it to fit into my Project. Once again thanks for your help. Many thanks
Hello Guys, I would like to ask if anyone has a VHDL example code of the vanilla TLP processing FSM Interface or any other idea, code which can help? I'm really struggling to get this Project going. Many thanks