I am a student and I recently learned how to create VHDL code for
displaying 4 digit time multiplexer on a coolrunner board. I am trying
to expand my knowledge and learn how to make the digits slide(left or
right) like they would on a billboard so when a digit slides left, it
would slide into the rightmost display. I am also trying to use the
decimal point on the display and how to make the system recognize where
the decimal point should be during sliding.
here is a sample of my shifter code:
entity ShifterSample is
Port ( clk : in std_logic;
reset : in std_logic;
data_i : in std_logic_vector (31 downto 0);
data_o : out std_logic_vector (31 downto 0));
end ShifterSample ;
architecture Behavioral of ShifterSample is
signal dataout_sig : std_logic_vector (31 downto 0);
begin
process (clk, reset, data_i, dataout_sig)
begin
if (reset = '1') then
dataout_sig <= "00010010001101000101011001111000";
--elsif (load ='1') then
dataout_sig<=data_i;
elsif (clk'event and clk = '1') then
dataout_sig <= dataout_sig(27 downto 0) & dataout_sig(31 downto 28);
end if ;
end process;
data_o<=dataout_sig;
data_o<=data_o(27 downto 0) & data_o(31 downto 28);
end Behavioral;
--
Also how would I link this in my main file:
------------------------------
entity time_multiplexer_main is
Port(clk : in std_logic;
reset : in std_logic;
data_in : in std_logic_vector(7 downto 0);
seg : out std_logic_vector(6 downto 0);
anode : inout std_logic_vector(3 downto 0));
end time_multiplexer_main;
architecture Behavioral of time_multiplexer_main is
component frequency_divider
port( clk: in std_logic;
reset: in std_logic;
clock1: inout std_logic);
end component;
component time_multiplexer_4digit
port(clk : in std_logic; --multiplexing clock(1 kHz)
reset : in std_logic; -- reset signal
display_value : in std_logic_vector(15 downto 0); --BCD digits to
be displayed
seg : out std_logic_vector(6 downto 0); --7 cathodes
anode : inout std_logic_vector(3 downto 0));
end component;
signal clk_1kHz: std_logic;-- this is a signal connecting the frequency
divider to the time multiplexer
--signal dataout_sig:
begin
cop1: frequency_divider
port map( clk=>clk,
reset=>reset,
clock1=>clk_1kHz);
cop3: time_multiplexer_4digit
port map( clk=>clk_1kHz,
reset=>reset,
DISPLAY_VALUE=>"0001001000110100",-- DISPLAY value signal
seg=>seg,
anode=>anode);
end Behavioral;