1 entity klausurCircuit is 2 end klausurCircuit; 3 4 architecture behavior of klausurCircuit is 5 signal a,b,c,d,e,f : bit; 6 begin 7 8 process (a,b) 9 begin 10 c <= not (a and b) after 6 ns; 11 d <= not (b or c) after 5 ns; 12 end process; 13 14 process (a,c) 15 begin 16 e <= transport c xor a after 5 ns; 17 end process; 18 19 end architecture behavior; what I don't understand is when you have in process(a,b) two signales what does that mean, when will the d change. Is what I made correct. Thank you for the explanation, I am new to Vhdl just trying to understand how it works. Best Regards
I think this is the inner meaning of this "Klausur". you will have to find out, when the signals operate and when not.
Oussama wrote: > 8 process (a,b) > 9 begin > 10 c <= not (a and b) after 6 ns; > 11 d <= not (b or c) after 5 ns; > 12 end process; Just as a hint: this process has an incomplete sensitivity list. 'c' is missing. So the solution is fairly tricky, because c changes 6ns after a or b has changed. But because c is missing in the sensitivity list the process is not evaluated again and d does not change. I recommend to ask your teacher about that sensitivity list... For the signal e you should calculate a xor-signal e' without delay. And then simply shift that e' for 5ns.
Lothar M. wrote: > Just as a hint: this process has an incomplete sensitivity list. Maybe this is intended since sampling is exactely simulated this way: The result is taken over only the point of time when the gated clock becomes active.
Mar. W. wrote: > the gated clock I can't see no clock of any kind in the whole design...
process (a,b) d <= not (b or c) after 5 ns; is a method to describe a gate because c is progressed into d only when b is active so any changes of c at others poits of time are not relevant. this way also clocks are simulated finally by converting the rising edge command into a signal which is active for one simulation step only
.. bad design practice
Klakx wrote: > .. bad design practice Because simulation result will not be the same like the behaviour of the synthesized design. So this "cute insider trick" is ugly coding no one will understand a half year later. Even the coder himself. If this kind of coding is teached anywhere then the school and the teacher is not worth the money! Lothar M. wrote: > I recommend to ask your teacher about that sensitivity list... I strongly recommend...