Forum: FPGA, VHDL & Verilog signales in processes VHDL

Author: Oussama (Guest)
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1 entity klausurCircuit is
2 end klausurCircuit;
4 architecture behavior of klausurCircuit is
5 signal a,b,c,d,e,f : bit;
6 begin
8 process (a,b)
9 begin
10 c <= not (a and b) after 6 ns;
11 d <= not (b or c) after 5 ns;
12 end process;
14 process (a,c)
15 begin
16 e <= transport c xor a after 5 ns;
17 end process;
19 end architecture behavior;

what I don't understand is when you have in process(a,b) two signales 
what does that mean, when will the d change. Is what I made correct.

Thank you for the explanation, I am new to Vhdl just trying to 
understand how it works.

Best Regards


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