How to combine bitstreams (thrid party IP cores) to use it in main design?
Guest
#5166365
In FPGA design when we buy Intellectual property (IP) from a vendor I assume they provide the IP core in a form of bitstream file. My question is how we actually combine these different bitstreams from different vendors and configure it in our system? Jaodat wrote: > I assume they provide the IP core in a form of bitstream file. What does this assumption base on? > they provide the IP core in a form of bitstream file. Then it is nearly useless because a bitstream is a programming file, its only useful to be loaded directly into exactly one type of FPGA. Usually a core consists of several (encrypted) netlist files and a HDL wrapper to invoke it in your top level design. > My question is how we actually combine these different bitstreams from > different vendors and configure it in our system? You know the different processing steps of your (unknwon) systen? Synthesize ... Translate ... Place&Route ... Programfile Generation? If no: read the manual. If yes: the wrapper goes to the synthesizer, the netlist usually to P&R.
Guest
#5167018
For Xilinx and Lattice FPGA you would typically receive a NGO black box object file with the interface defined in the wrapper source that Lothar already mentioned. Then there's not much difference from using a source or black box component, from the programmer's perspective. Just that you can't stick the NGO into simulation. ReplyPlease log in before posting. |