Not showing where is the error

Rock B. OP #5154018
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Hello, My code is not running , it says synthesys XST failed
but it doesnt say why.
i fixed every error shown before but now its not showing whats wrong

Thanks


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library IEEE;

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use IEEE.STD_LOGIC_1164.ALL;

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use IEEE.STD_LOGIC_arith.ALL;

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use IEEE.STD_LOGIC_unsigned.ALL;

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-- Uncomment the following library declaration if using

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-- arithmetic functions with Signed or Unsigned values

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--use IEEE.NUMERIC_STD.ALL;

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-- Uncomment the following library declaration if instantiating

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-- any Xilinx primitives in this code.

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--library UNISIM;

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--use UNISIM.VComponents.all;

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entity voting_machine is

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Port

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   (

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    clk: in std_logic;

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    reset: in std_logic;

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    party1: in std_logic;

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    party2: in std_logic;

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    party3: in std_logic;

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    select_party: in std_logic;

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    count1_op : out std_logic_vector(5 downto 0);

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    count2_op : out std_logic_vector(5 downto 0);

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    count3_op : out std_logic_vector(5 downto 0)

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   );

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end voting_machine;

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architecture Behavioral of voting_machine is

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signal count1,count2,count3: std_logic_vector(5 downto 0);

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signal state: std_logic_vector(5 downto 0);

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constant initial: std_logic_vector(5 downto 0):="000001";

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constant check: std_logic_vector(5 downto 0):="000010";

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constant party1_state: std_logic_vector(5 downto 0):="000100";

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constant party2_state: std_logic_vector(5 downto 0):="001000";

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constant party3_state: std_logic_vector(5 downto 0):="010000";

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constant done: std_logic_vector(5 downto 0):="100000";

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begin

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process( clk, party1, party2, party3,reset)

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begin

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      if (reset='1') then

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        count1<=(others=>'0');

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       count2<=(others=>'0');

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       count3<=(others=>'0');

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       state<=initial;

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       elsif (rising_edge(clk) and reset='0') then

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       case state is

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          when initial=>

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          --NSL

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            if (party1='1' or party2='1' or party3='1') then

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                state<=check;

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            else

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                state<=initial;

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          --OFL  

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                 end if;

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            when check =>  

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                   --NSL

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                      if(party1='1') then 

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                         state<=party1_state;

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                      elsif (party2='1') then 

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                   state<=party2_state;

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                elsif (party3='1') then

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                          state<=party3_state;             

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               else

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                   state<=check;

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                end if;

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                    --OFL

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                when party1_state =>

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             --NSL

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            if (select_party='1') then 

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                 state<=done;

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             else

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                       state<=party1_state;

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                end if;

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            --OFL

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            count1<=count1 + 1;

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            when party2_state =>

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             --NSL

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            if (select_party='1') then 

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                 state<=done;

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             else

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                       state<=party2_state;

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                end if;

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            --OFL

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            count2<=count2 + 1;

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            when party3_state =>

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             --NSL

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            if (select_party='1') then 

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                 state<=done;

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             else

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                       state<=party3_state;

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                end if;

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            --OFL

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            count3<=count3 + 1;

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            when done =>

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               --NSL

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                 state<=initial;

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              --OFL

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             when others=>

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               state<=initial;

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        end case;

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      end if;

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  end process;

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 count1_op<=count1;

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 count2_op<=count2;

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 count3_op<=count3;

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end Behavioral;
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loi le Guest #5154535
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You are implementing the Finite State Machine and your code is not good. 
Try to separate the Next state combinational logic, Sequential logic, 
and output combinational logic. You mixed it up and it looked messed up.
Follow this FSM example in VHDL:
http://www.fpga4student.com/2017/09/vhdl-code-for-moore-fsm-sequence-detector.html
or Verilog FSM here:
http://www.fpga4student.com/2017/09/verilog-code-for-moore-fsm-sequence-detector.html
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Lothar M. Moderator (Company: Titel) #5154564
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loi le wrote:
> Try to separate the Next state combinational logic, Sequential logic,
> and output combinational logic. You mixed it up and it looked messed up
There are two major ways to design FSM: the One-Process style and the 
traditional Two-Process style.

Both of them have advantages and disadvantages. The best with the 
One-Process style (beside being more compact and less "chatty") is: you 
will never ever get a combinatorial loop.

But of course one should understand what he's doing. And here we have 
two design flaws. One is the sensitivity list with much much signals in 
it. clk and reset would be enough. And then the reset='0' behind the 
clk'event. Why that?

Rock B. wrote:
> XST failed. but it doesnt say why.
Absolutely no message? The one and only message is "XST failed"?
Why don't you simply copy the whole message log in the edit box here?
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Bitwurschtler Guest #5154599
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IMHO this is strange coding for the synthesize tool:


1
    if (reset='1') then

2
        count1<=(others=>'0');

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       count2<=(others=>'0');

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       count3<=(others=>'0');

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       state<=initial;

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     elsif (rising_edge(clk) and reset='0') then  -- combinatorik at clock tree



replace the elsif condition with
1
elsif rising_edge(clk) then

and run Synthesis again
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Bitwurschtler Guest #5155000
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Lothar M. wrote:
> Bitwurschtler wrote:
>> elsif (rising_edge(clk) and reset='0') then
> Usually this shouldn't rise problems, as it's only a clock enable. But
> it's not the "normal"  way and hey, who knows?

Well, some FPGA architectures are simply not intended for using the same 
signal as asynchronous and synchronous control Signal (here 'reset' is 
used as high active async reset and low active sync clock enable. 
Despite the Standard (xilinx) template for clock enable is
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if reset = '1' then

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-- ..

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elsif rissing_edge(clk) then

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 if  reset = '0' then

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-- ..

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 end if;

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end if:


https://www.xilinx.com/support/documentation/white_papers/wp275.pdf

VHDL Syntax for Synthesis is vendor specific, so there is a "good 
chance" that

1
 

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elsif (rising_edge(clk) and reset='0') then

 is translated into a gated clock ant not a clock enable.
http://vhdlguru.blogspot.de/2010/04/what-is-gated-clock-and-how-it-reduces.html


I am also wondering how STA is handling a (assumed) asynchronous clock 
enable.
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Lothar M. Moderator (Company: Titel) #5155326
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Bitwurschtler wrote:
> VHDL Syntax for Synthesis is vendor specific, so there is a "good
> chance" that
> elsif (rising_edge(clk) and reset='0') then
>  is translated into a gated clock ant not a clock enable.
With all the toolchains I used up to now I got the same result just like 
the test there:
http://www.lothar-miller.de/s9y/categories/6-Clock-Enable
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