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Forum: FPGA, VHDL & Verilog Not showing where is the error


Author: Rock Bog (rocko445)
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Hello, My code is not running , it says synthesys XST failed
but it doesnt say why.
i fixed every error shown before but now its not showing whats wrong

Thanks

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity voting_machine is
Port
   (
    clk: in std_logic;
    reset: in std_logic;
    party1: in std_logic;
    party2: in std_logic;
    party3: in std_logic;
    select_party: in std_logic;
    count1_op : out std_logic_vector(5 downto 0);
    count2_op : out std_logic_vector(5 downto 0);
    count3_op : out std_logic_vector(5 downto 0)
   );
    
end voting_machine;

architecture Behavioral of voting_machine is

signal count1,count2,count3: std_logic_vector(5 downto 0);
signal state: std_logic_vector(5 downto 0);
constant initial: std_logic_vector(5 downto 0):="000001";
constant check: std_logic_vector(5 downto 0):="000010";
constant party1_state: std_logic_vector(5 downto 0):="000100";
constant party2_state: std_logic_vector(5 downto 0):="001000";
constant party3_state: std_logic_vector(5 downto 0):="010000";
constant done: std_logic_vector(5 downto 0):="100000";


begin

process( clk, party1, party2, party3,reset)

begin

      if (reset='1') then
        count1<=(others=>'0');
       count2<=(others=>'0');
       count3<=(others=>'0');
       state<=initial;
       elsif (rising_edge(clk) and reset='0') then
      
       case state is
            
          when initial=>
          --NSL
            if (party1='1' or party2='1' or party3='1') then
                state<=check;
              
            else
                state<=initial;
          --OFL  
                 end if;
            when check =>  
                   --NSL
                      if(party1='1') then 
                         state<=party1_state;
                      elsif (party2='1') then 
                   state<=party2_state;
                elsif (party3='1') then
                          state<=party3_state;             
               else
                   state<=check;
                end if;
                    --OFL
                when party1_state =>
             --NSL
            if (select_party='1') then 
                 state<=done;
             else
                       state<=party1_state;
                
                end if;
            --OFL
            count1<=count1 + 1;
            
            
            when party2_state =>
             --NSL
            if (select_party='1') then 
                 state<=done;
             else
                       state<=party2_state;
                
                end if;
            --OFL
            count2<=count2 + 1;
            
            when party3_state =>
             --NSL
            if (select_party='1') then 
                 state<=done;
             else
                       state<=party3_state;
                
                end if;
            --OFL
            count3<=count3 + 1;
            
            when done =>
               --NSL
                 state<=initial;
              --OFL
             when others=>
               state<=initial;
        end case;
      end if;
    
  end process;
 count1_op<=count1;
 count2_op<=count2;
 count3_op<=count3;
            
end Behavioral;


Author: loi le (Guest)
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You are implementing the Finite State Machine and your code is not good. 
Try to separate the Next state combinational logic, Sequential logic, 
and output combinational logic. You mixed it up and it looked messed up.
Follow this FSM example in VHDL:
http://www.fpga4student.com/2017/09/vhdl-code-for-...
or Verilog FSM here:
http://www.fpga4student.com/2017/09/verilog-code-f...

Author: Lothar Miller (lkmiller) (Moderator)
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loi le wrote:
> Try to separate the Next state combinational logic, Sequential logic,
> and output combinational logic. You mixed it up and it looked messed up
There are two major ways to design FSM: the One-Process style and the 
traditional Two-Process style.

Both of them have advantages and disadvantages. The best with the 
One-Process style (beside being more compact and less "chatty") is: you 
will never ever get a combinatorial loop.

But of course one should understand what he's doing. And here we have 
two design flaws. One is the sensitivity list with much much signals in 
it. clk and reset would be enough. And then the reset='0' behind the 
clk'event. Why that?

Rock B. wrote:
> XST failed. but it doesnt say why.
Absolutely no message? The one and only message is "XST failed"?
Why don't you simply copy the whole message log in the edit box here?

Author: Bitwurschtler (Guest)
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IMHO this is strange coding for the synthesize tool:

    if (reset='1') then
        count1<=(others=>'0');
       count2<=(others=>'0');
       count3<=(others=>'0');
       state<=initial;
     elsif (rising_edge(clk) and reset='0') then  -- combinatorik at clock tree



replace the elsif condition with
elsif rising_edge(clk) then
and run Synthesis again

Author: Lothar Miller (lkmiller) (Moderator)
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Bitwurschtler wrote:
> elsif (rising_edge(clk) and reset='0') then
Usually this shouldn't rise problems, as it's only a clock enable. But 
it's not the "normal"  way and hey, who knows?

: Edited by Moderator
Author: Bitwurschtler (Guest)
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Lothar M. wrote:
> Bitwurschtler wrote:
>> elsif (rising_edge(clk) and reset='0') then
> Usually this shouldn't rise problems, as it's only a clock enable. But
> it's not the "normal"  way and hey, who knows?

Well, some FPGA architectures are simply not intended for using the same 
signal as asynchronous and synchronous control Signal (here 'reset' is 
used as high active async reset and low active sync clock enable. 
Despite the Standard (xilinx) template for clock enable is
if reset = '1' then
-- ..
elsif rissing_edge(clk) then
 if  reset = '0' then
-- ..
 end if;
end if:

https://www.xilinx.com/support/documentation/white...

VHDL Syntax for Synthesis is vendor specific, so there is a "good 
chance" that
 
elsif (rising_edge(clk) and reset='0') then
 is translated into a gated clock ant not a clock enable.
http://vhdlguru.blogspot.de/2010/04/what-is-gated-...


I am also wondering how STA is handling a (assumed) asynchronous clock 
enable.

Author: Lothar Miller (lkmiller) (Moderator)
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Bitwurschtler wrote:
> VHDL Syntax for Synthesis is vendor specific, so there is a "good
> chance" that
> elsif (rising_edge(clk) and reset='0') then
>  is translated into a gated clock ant not a clock enable.
With all the toolchains I used up to now I got the same result just like 
the test there:
http://www.lothar-miller.de/s9y/categories/6-Clock-Enable

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