hi, please anyone tell the difference between the below if statement
1 | always @(posedge cpld_refclk) |
2 | begin
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3 | if(!pon_rst_n) |
4 | begin
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5 | req_rst_r <= 1; |
1 | always @(posedge cpld_refclk) |
2 | begin
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3 | if(!v3v3_pgood) |
4 | begin
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5 | tier_cnt <= 10'd0; |
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Forum: FPGA, VHDL & Verilog Verilog if statementhi, please anyone tell the difference between the below if statement
Hareesh M. wrote: > please anyone tell the difference between the below if statement I see two different signals. They may have a different function also. Consult the spec of those signals or the schematics for further information. Lothar M. wrote: > Hareesh M. wrote: >> please anyone tell the difference between the below if statement > I see two different signals. They may have a /different function/ > also. > Consult the spec of those signals or the schematics for further > information. pon_rst_n is a active low signal and v3v3_pgood is a active high signal Hareesh M. wrote: > pon_rst_n is a active low signal and v3v3_pgood is a active high signal From the very same source/pin? i actually need to know the statement
and
. if i have a pon_rst_n = 1 what will be the output and if i have a v3v3_pgood = 0 what will be the result. Hareesh M. wrote: > . if i have a pon_rst_n = 1 what will be the output and if i have a The output is what's in the else clause if there is one (you did not show), if there's no else req_rst_r stays the previous stored value. > v3v3_pgood = 0 what will be the result. the result will be tier_cnt <= 10'd0; on the next up edge Please log in before posting. Registration is free and takes only a minute.
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