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Forum: FPGA, VHDL & Verilog Verilog if statement


Author: Hareesh Mohanan (Company: Mindteck) (hareeshp)
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hi,
please anyone tell the difference between the below if statement
always @(posedge cpld_refclk)
begin
  if(!pon_rst_n)
  begin
    req_rst_r <= 1;
always @(posedge cpld_refclk)
begin
  if(!v3v3_pgood)
  begin
    tier_cnt <= 10'd0;

Author: Lothar Miller (lkmiller) (Moderator)
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Hareesh M. wrote:
> please anyone tell the difference between the below if statement
I see two different signals. They may have a different function 
also.
Consult the spec of those signals or the schematics for further 
information.

Author: Hareesh Mohanan (Company: Mindteck) (hareeshp)
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Lothar M. wrote:
> Hareesh M. wrote:
>> please anyone tell the difference between the below if statement
> I see two different signals. They may have a /different function/
> also.
> Consult the spec of those signals or the schematics for further
> information.

pon_rst_n is a active low signal and v3v3_pgood is a active high signal

Author: Lothar Miller (lkmiller) (Moderator)
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Hareesh M. wrote:
> pon_rst_n is a active low signal and v3v3_pgood is a active high signal
From the very same source/pin?

Author: Hareesh Mohanan (Company: Mindteck) (hareeshp)
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i actually need to know the statement
 if(!pon_rst_n)
 and
 if(!v3v3_pgood)
. if i have a pon_rst_n = 1 what will be the output and if i have a 
v3v3_pgood = 0 what will be the result.

Author: Johann Klammer (Guest)
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Hareesh M. wrote:
> . if i have a pon_rst_n = 1 what will be the output and if i have a

The output is what's in the else clause if there is one (you did not 
show), if there's no else req_rst_r stays the previous stored value.

> v3v3_pgood = 0 what will be the result.

the result will be
tier_cnt <= 10'd0;
on the next up edge

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