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Forum: FPGA, VHDL & Verilog VHDL error when else


Author: Hareesh Mohanan (Company: Mindteck) (hareeshp)
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hi,
 library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity req is
  port(fpga_clk: in std_logic;
      evt_pwr_en: in std_logic;
      ifc_we_n : inout std_logic;
      hreset_n : inout std_logic;
      pwr_rst_n :  in std_logic;
      ifc_ad8_15 : inout std_logic_vector( 7 downto 0);
      sensevdd_en_n : out std_logic;
      iopwr_en : out std_logic;
      iopwr_en_n : out std_logic;
      ddrpwr_en : out std_logic;
      ddrpwr_en_n : out std_logic;  
      vdd_en : out std_logic;
      vdd_en_n : out std_logic;
      vcore_en : out std_logic;
      evt_pwr_ok : out std_logic;
      v3v3_pgood: in std_logic);
end req;
architecture power of req is
signal tier_cnt: std_logic_vector(19 downto 0);
signal tier_cnt_int:std_logic;
signal tier : std_logic_vector(3 downto 0);
signal vcore_en_cnt: std_logic_vector(9 downto 0);
signal pwr_gd_cnt : std_logic_vector(19 downto 0);
signal pwr_ok_cnt:  std_logic_vector(19 downto 0);
signal rst_holf_f : std_logic;
signal req_rst_r : std_logic;
signal req_cop_trst_r  : std_logic;
signal cfg_egn_use0 : std_logic;
signal cpu_rst_n : std_logic;
signal pwr_rst_cnt : std_logic_vector(9 downto 0);
signal rcw_config_word : std_logic_vector( 7 downto 0);
begin

pon_rst_n <= (pwr_rst_n  when pwr_ok_cnt(19) = '1' else '1') when v3v3_pgood and pwr_gd_cnt(19) = '1' else pwr_rst_n;

process(tier_cnt_int)
begin
  if(rising_edge(tier_cnt_int)) then
    if(v3v3_pgood = '0') then
      tier_cnt(3 downto 0)  <= "1111";
    else
      tier(3) <= tier(2);
      tier(2) <= tier(1);
      tier(1) <= tier(0);
      tier(0) <= evt_pwr_en;
    end if;
  end if;
end process;

process(fpga_clk) 
begin
  if(rising_edge(fpga_clk)) then
    if(v3v3_pgood = '0') then
      vcore_en_cnt <= (others => '0');
    else
      if(vcore_en_cnt > "0110000000") then
        vcore_en_cnt <= "1111111111";
      else
        vcore_en_cnt <= vcore_en_cnt + 1;
      end if;
    end if;
  end if;
end process;
process(fpga_clk) 
begin
  if(rising_edge(fpga_clk)) then
    if(v3v3_pgood = '0') then
      pwr_gd_cnt <= (others => '0');
    else
      if(pwr_gd_cnt > x"08000") then
        pwr_gd_cnt <= (others => '1');
      else
        pwr_gd_cnt <= pwr_gd_cnt + 1;
      end if;
    end if;
  end if;
end process;

process(fpga_clk) 
begin
  if(rising_edge (fpga_clk)) then
    if( (not(cpu_rst_n) or (rst_holf_f) or (hreset_n and (not(req_rst_r)) and req_cop_trst_r  ))= '1') then
      cfg_egn_use0 <= ifc_we_n;
    end if;
  end if;
end process;

process(fpga_clk)
begin
  if(rising_edge(fpga_clk)) then
    if(pwr_rst_n = '0') then
      rcw_config_word <= ifc_ad8_15;
    end if;
  end if;
end process;  
end power; 

the code above shows an error like

Error (10500): VHDL syntax error at req.vhd(38) near text "when"; 
expecting ")", or ","

Author: user (Guest)
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because for when statement there is no (), here is an example:

a <= '1' when c = '1' else
     '0' when d = '1' else
     '0';

Author: Hareesh Mohanan (Company: Mindteck) (hareeshp)
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user wrote:
> because for when statement there is no (), here is an example:
>
> a <= '1' when c = '1' else
>      '0' when d = '1' else
>      '0';

actually in the above code, pon_rst_n will be pwr_rst_n based on the 
value of v3v3_pgood and pwr_gd_cnt(19). But before assignment i have to 
check pwr_rst_n based on the values of pwr_ok_cnt(19).

Author: Lothar Miller (lkmiller) (Moderator)
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Hareesh M. wrote:
> the code above shows an error like
A hint: use your text editor to format and indent your code. Then you 
see such things very easy...
pon_rst_n <= (pwr_rst_n  when pwr_ok_cnt(19) = '1'                  else
             '1')        when v3v3_pgood and pwr_gd_cnt(19) = '1'   else
             pwr_rst_n;
Easy to see: one useless '(' in the first line and one wrong ')' in the 
second line...

And this is almost unreadable:
    if( (not(cpu_rst_n) or (rst_holf_f) or (hreset_n and (not(req_rst_r)) and req_cop_trst_r  ))= '1') then
Are you sure it is doing what you want?
I could write it this way:
    if  cpu_rst_n='0'  or
        rst_holf_f='1' or
        hreset_n='1' and req_rst_r='0' and req_cop_trst_r='1' then
In my opinion now everybody recogizes what he will get with one short 
blink...

: Edited by Moderator
Author: Hareesh Mohanan (Company: Mindteck) (hareeshp)
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Lothar M. wrote:
> Hareesh M. wrote:
>> the code above shows an error like
> A hint: use your text editor to format and indent your code. Then you
> see such things very easy...
>
> pon_rst_n <= (pwr_rst_n  when pwr_ok_cnt(19) = '1'                  else
>              '1')        when v3v3_pgood and pwr_gd_cnt(19) = '1'   else
>              pwr_rst_n;
> 
>
> And this is almost unreadable:
>
>     if( (not(cpu_rst_n) or (rst_holf_f) or (hreset_n and 
> (not(req_rst_r)) and req_cop_trst_r  ))= '1') then
> 
> Are you sure it is doing what you want?
> I could write it this way:
>
>     if  cpu_rst_n='0'  or
>         rst_holf_f='1' or
>         hreset_n='1' and req_rst_r='0' and req_cop_trst_r='1' then
> 
> In my opinion now everybody recogizes what he will get with one short
> blink...

i corrected the when else statement error, but now it is showing 
"v3v3_pgood" does not agree with "boolean" type.

and thanks for you help that "if" statement.

Author: Lothar Miller (lkmiller) (Moderator)
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Hareesh M. wrote:
> i corrected the when else statement error, but now it is showing
> "v3v3_pgood" does not agree with "boolean" type.
Try this:
pon_rst_n <= pwr_rst_n  when pwr_ok_cnt(19)='1'                      else
             '1'        when v3v3_pgood='1' and pwr_gd_cnt(19)='1'   else
             pwr_rst_n;

Hareesh M. wrote:
> but now it is showing "v3v3_pgood" does not agree with "boolean" type.
Please start thinking for yourself about those messages before 
posting. Usually such errors are easy to locate...
We solved this "problem" about different types (std_logic ist not 
boolean) a few days ago. Do you remember?

: Edited by Moderator
Author: Hareesh Mohanan (Company: Mindteck) (hareeshp)
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hi,
i still have some issue with when else statement,
 ifc_ad8_15 <= "ZZZZZZZZ" when cpu_rst_n and (not rst_hold_f) and (req_rst_r when (req_md_r = "11") else '1') = '1' 
          else rcw_src(0 to 7) when boot_override_r = '1' else "ZZZZZZZZ"; 

showing the same error
Error (10500): VHDL syntax error at req.vhd(556) near text "when"; 
expecting ")", or ","
Error (10500): VHDL syntax error at req.vhd(556) near text ")"; 
expecting ";"

Author: Lothar Miller (lkmiller) (Moderator)
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Get all the parenthesis right and correct the logical problems leading 
to syntax problems, then it will be ok.

See, what I wrote in the post before your last (that about "start 
thinking yourself" and remind the comment about "readability" of code). 
It will help to solve that problem...

: Edited by Moderator

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