EmbDev.net

Forum: FPGA, VHDL & Verilog VHDL GATE and DELAYS


Author: MB (Guest)
Posted on:

Rate this post
0 useful
not useful
Hello, below is the code I currently have


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity \AND\ is
  port(A,B: in std_logic; C: out std_logic);
end \AND\;



architecture \AND\ of \AND\ is
begin
  process(A,B)
  begin
    if (A = '1' and B = '1') then
      C<='1';
    else
      C<='0';
    end if;
  end process;


end \AND\;

This is what I'm trying to accomplish

Create a design named "gate_lib".  In this design, create two input VHDL 
models for each of the basic gates (AND, OR, NAND, NOR, XOR, XNOR) and a 
one input NOT gate. Each model should be in its own separate file 
defined with its own custom entity/architecture.  Furthermore, implement 
the functionality of each gate using a process with if statements (see 
§2.5 from book) and use signals from the std_logic_1164library.  All 
gates except XOR and XNOR have a propagation delay of 100 ps.  XOR and 
XNOR gates have a propagation delay of 150 ps.  Test your models 
individually by creating a waveform using the Aldec Waveform 
Viewer/Editor.  Be sure your test includes all input combinations for 
each gate.


The code runs fine and produces the right output on the waveform 
simulation (C), but when the delay is added of 100 ps in the if 
statements, the out put cuts to zero after 100ps and reamins at 0 for 
the rest of the simulation. Could someone point me in the right 
direction for the delays?:)

Author: Achim S. (Guest)
Posted on:

Rate this post
0 useful
not useful
So the code you show works without problems?

And the code with delays behaves differently than expected? Then you 
should of course show us the code with delays, that makes the problems.

How should we recognize the problems of the problematic code if you show 
us the error-free code instead?

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
Achim S. wrote:
> Then you should of course show us the code with delays, that makes the
> problems.
And the related testbench also...

MB wrote:
> Test your models individually by creating a waveform using the Aldec
> Waveform Viewer/Editor.
Uhmmm, I see: there is no testbench. What a incredible pity (what school 
is that?).
Then show us a screenshot of your debugging session.

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig