Hello, below is the code I currently have
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity \AND\ is
port(A,B: in std_logic; C: out std_logic);
end \AND\;
architecture \AND\ of \AND\ is
begin
process(A,B)
begin
if (A = '1' and B = '1') then
C<='1';
else
C<='0';
end if;
end process;
end \AND\;
This is what I'm trying to accomplish
Create a design named "gate_lib". In this design, create two input VHDL
models for each of the basic gates (AND, OR, NAND, NOR, XOR, XNOR) and a
one input NOT gate. Each model should be in its own separate file
defined with its own custom entity/architecture. Furthermore, implement
the functionality of each gate using a process with if statements (see
§2.5 from book) and use signals from the std_logic_1164library. All
gates except XOR and XNOR have a propagation delay of 100 ps. XOR and
XNOR gates have a propagation delay of 150 ps. Test your models
individually by creating a waveform using the Aldec Waveform
Viewer/Editor. Be sure your test includes all input combinations for
each gate.
The code runs fine and produces the right output on the waveform
simulation (C), but when the delay is added of 100 ps in the if
statements, the out put cuts to zero after 100ps and reamins at 0 for
the rest of the simulation. Could someone point me in the right
direction for the delays?:)