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Verilog code
von Hareesh M. (Company: Mindteck) (hareeshp)

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hi
please anyone tell me the logic in the below
1
 ifc_ad8_15[0:7] = (cpu_rst_n & (~rst_hold_f) &  ((req_md_r == 2'b11)? req_rst_r : 1'b1))? 8'bz : (boot_override_r? rcw_src_r[0:7] : 8'bz);

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Re: Verilog code
von Andreas (Guest)

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Ask Google, and see here:

https://stackoverflow.com/questions/12336139/verilog-question-mark-operator


It's an if-else construct.


Best Regards,
Andreas

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Re: Verilog code
von Hareesh M. (Company: Mindteck) (hareeshp)

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Andreas wrote:
> Ask Google, and see here:
>
> https://stackoverflow.com/questions/12336139/verilog-question-mark-operator
>
>
> It's an if-else construct.
>
>
> Best Regards,
> Andreas

actually i need to convert the above verilog logic onto vhdl. And i 
converted as below
1
 ifc_ad8_15 <= "ZZZZZZZZ" when (cpu_rst_n and (not(rst_hold_f)) and (req_rst_r when (req_md_r = "11") else '1'))else (rcw_src(7 dwonto 0) when boot_override_r else "ZZZZZZZZ") ;


but it is showing error

Error (10500): VHDL syntax error at req.vhd(137) near text "when"; 
expecting ")", or ","
Error (10500): VHDL syntax error at req.vhd(137) near text ")"; 
expecting ";"

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Re: Verilog code
von Hareesh M. (Company: Mindteck) (hareeshp)

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Andreas wrote:
> Ask Google, and see here:
>
> https://stackoverflow.com/questions/12336139/verilog-question-mark-operator
>
>
> It's an if-else construct.
>
>
> Best Regards,
> Andreas

actually this signal assignment has to be outside of the "process" so we 
cant use if else.

: Edited by User
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