Verilog code

Andreas wrote:
> Ask Google, and see here:
>
> https://stackoverflow.com/questions/12336139/verilog-question-mark-operator
>
>
> It's an if-else construct.
>
>
> Best Regards,
> Andreas

actually i need to convert the above verilog logic onto vhdl. And i 
converted as below

1

 ifc_ad8_15 <= "ZZZZZZZZ" when (cpu_rst_n and (not(rst_hold_f)) and (req_rst_r when (req_md_r = "11") else '1'))else (rcw_src(7 dwonto 0) when boot_override_r else "ZZZZZZZZ") ;

but it is showing error

Error (10500): VHDL syntax error at req.vhd(137) near text "when"; 
expecting ")", or ","
Error (10500): VHDL syntax error at req.vhd(137) near text ")"; 
expecting ";"

Andreas wrote:
> Ask Google, and see here:
>
> https://stackoverflow.com/questions/12336139/verilog-question-mark-operator
>
>
> It's an if-else construct.
>
>
> Best Regards,
> Andreas

actually this signal assignment has to be outside of the "process" so we 
cant use if else.