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Forum: FPGA, VHDL & Verilog Counter in the existing program


Counter in the existing program
von Hareesh M. (Company: Mindteck) (hareeshp)

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hi,
i have a vhdl code written below,
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library ieee;

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use ieee.std_logic_1164.all;

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use ieee.numeric_std.all;

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use ieee.std_logic_unsigned.all;

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  entity powerseq is

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  port(      fpga_clk: in std_logic;

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          EN_1v  : out std_logic;    -- Enabling signal of 1V

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          EN_1v8  : out std_logic;  -- Enabling signal of 1V8

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          EN_1v2 : out std_logic;    -- Enabling signal of 1V2

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          EN_1v35 : out std_logic;  -- Enabling signal of 1V35

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          EN_2v5 : out std_logic;    -- Enabling signal of 2V5

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          EN_3v3 : out std_logic;    -- Enabling signal of 3V3  

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          EN_V1P0 : out std_logic;  -- Enabling signal of V1P0  

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          PGOOD_1v8 : in std_logic:= '1';   -- Power Good Signal 1V8

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          PGOOD_1v35 : in std_logic:= '1';  -- Power Good Signal 1V35

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          PGOOD_2v5 : in std_logic:= '1';  -- Power Good Signal 2V5

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          PGOOD_3v3 : in std_logic:= '1';  -- Power Good Signal 3V3  

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          PGOOD_1v  : in std_logic:= '1';  -- Power Good Signal 1V

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          PGOOD_1v2 : in std_logic:= '1';  -- Power Good Signal 1V2

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          poreset_b  : out std_logic;

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          PGOOD_V1P0 : in std_logic:= '1'  -- Power Good Signal V1P0

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          );

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 end powerseq;

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 architecture behav of powerseq is

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 signal pon_state : integer := 0;

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 signal counter : integer := 0;

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 begin

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  process(fpga_clk) 

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    begin

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      if(rising_edge(fpga_clk)) then

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        if(pon_state = 0) then 

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            poreset_b  <= '1';

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            EN_1v8  <= '1';

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            EN_1v35 <= '1';

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            EN_2v5  <= '1';

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            EN_3v3  <= '1';

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            pon_state <= 1;

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            EN_1v <= '0';

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            EN_V1P0 <= '0';

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            En_1v2<= '0';

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        end if;

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        if(pon_state =  1) then

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          if((PGOOD_1v8 and PGOOD_1v35 and PGOOD_2v5 and PGOOD_3v3 )='1') then --checking whether the PGOOD signals are stable  

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            EN_1v <= '1';

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            EN_V1P0 <= '1';

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            poreset_b<= '0';

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            pon_state <= 2;

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          end if;

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          if (pon_state = 2) then

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            if((PGOOD_1v and PGOOD_V1P0)= '1') then --checking whether the PGOOD signals are stable.

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            En_1v2<= '1';

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            pon_state <= 3;

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          end if;

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          end if;

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      end if;

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    end process;

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  end behav;


in the above code how i can add 2 sec delay before checking the
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 if((PGOOD_1v8 and PGOOD_1v35 and PGOOD_2v5 and PGOOD_3v3 )='1')

.I have assigned all the signals to leds. and need to see the delay in 
the output leds.

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Re: Counter in the existing program
von King Julian (Guest)

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Insert another state between 1 and 2 where you have a counter for 2 sec

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Re: Counter in the existing program
von Hareesh M. (Company: Mindteck) (hareeshp)

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King Julian wrote:
> Insert another state between 1 and 2 where you have a counter for 2 sec

actually by adding a counter will solve this problem right?

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Re: Counter in the existing program
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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Hareesh M. wrote:
> i have a vhdl code written below,
> use ieee.numeric_std.all;
> use ieee.std_logic_unsigned.all;
Never use the obsolete std_logic_arith and its std_logic_(un)signed 
together with the numeric_std. You will get strange behaviour and error 
messages due to double type definitions.

Hareesh M. wrote:
> actually by adding a counter will solve this problem right?
Yes, allmost all times in FPGA are realized by counters...

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