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Forum: FPGA, VHDL & Verilog Counter in the existing program


Author: Hareesh Mohanan (Company: Mindteck) (hareeshp)
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hi,
i have a vhdl code written below,
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
  entity powerseq is
  port(      fpga_clk: in std_logic;
          EN_1v  : out std_logic;    -- Enabling signal of 1V
          EN_1v8  : out std_logic;  -- Enabling signal of 1V8
          EN_1v2 : out std_logic;    -- Enabling signal of 1V2
          EN_1v35 : out std_logic;  -- Enabling signal of 1V35
          EN_2v5 : out std_logic;    -- Enabling signal of 2V5
          EN_3v3 : out std_logic;    -- Enabling signal of 3V3  
          EN_V1P0 : out std_logic;  -- Enabling signal of V1P0  
          PGOOD_1v8 : in std_logic:= '1';   -- Power Good Signal 1V8
          PGOOD_1v35 : in std_logic:= '1';  -- Power Good Signal 1V35
          PGOOD_2v5 : in std_logic:= '1';  -- Power Good Signal 2V5
          PGOOD_3v3 : in std_logic:= '1';  -- Power Good Signal 3V3  
          PGOOD_1v  : in std_logic:= '1';  -- Power Good Signal 1V
          PGOOD_1v2 : in std_logic:= '1';  -- Power Good Signal 1V2
          poreset_b  : out std_logic;
          PGOOD_V1P0 : in std_logic:= '1'  -- Power Good Signal V1P0
          );
 end powerseq;
 architecture behav of powerseq is
 signal pon_state : integer := 0;
 signal counter : integer := 0;
 begin
  process(fpga_clk) 
    begin
    
      if(rising_edge(fpga_clk)) then
        if(pon_state = 0) then 
            poreset_b  <= '1';
            EN_1v8  <= '1';
            EN_1v35 <= '1';
            EN_2v5  <= '1';
            EN_3v3  <= '1';
            pon_state <= 1;
            EN_1v <= '0';
            EN_V1P0 <= '0';
            En_1v2<= '0';
        end if;
        if(pon_state =  1) then
          if((PGOOD_1v8 and PGOOD_1v35 and PGOOD_2v5 and PGOOD_3v3 )='1') then --checking whether the PGOOD signals are stable  
            EN_1v <= '1';
            EN_V1P0 <= '1';
            poreset_b<= '0';
            pon_state <= 2;
          end if;
          if (pon_state = 2) then
            if((PGOOD_1v and PGOOD_V1P0)= '1') then --checking whether the PGOOD signals are stable.
            En_1v2<= '1';
            pon_state <= 3;
          end if;
          end if;
      end if;
    end process;
  end behav;

in the above code how i can add 2 sec delay before checking the
 if((PGOOD_1v8 and PGOOD_1v35 and PGOOD_2v5 and PGOOD_3v3 )='1') 
.I have assigned all the signals to leds. and need to see the delay in 
the output leds.

Author: King Julian (Guest)
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Insert another state between 1 and 2 where you have a counter for 2 sec

Author: Hareesh Mohanan (Company: Mindteck) (hareeshp)
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King Julian wrote:
> Insert another state between 1 and 2 where you have a counter for 2 sec

actually by adding a counter will solve this problem right?

Author: Lothar Miller (lkmiller) (Moderator)
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Hareesh M. wrote:
> i have a vhdl code written below,
> use ieee.numeric_std.all;
> use ieee.std_logic_unsigned.all;
Never use the obsolete std_logic_arith and its std_logic_(un)signed 
together with the numeric_std. You will get strange behaviour and error 
messages due to double type definitions.

Hareesh M. wrote:
> actually by adding a counter will solve this problem right?
Yes, allmost all times in FPGA are realized by counters...

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