EmbDev.net

Forum: FPGA, VHDL & Verilog VHDL Code error


Author: Hareesh Mohanan (Company: Mindteck) (hareeshp)
Posted on:

Rate this post
0 useful
not useful
hi,
i have an if statement in my code
if(a and (not b) and c = '1') then
          output <= '1';
      else
           output <= '0';
       end if;

a, b, and c are internal signal of type std_logic;
output is signal out std_logic;

when compile this code it is showing an error

Error (10476): VHDL error at PowerSeq1.vhd(486): type of identifier "a" 
does not agree with its usage as "boolean" type

Author: C. A. Rotwang (Guest)
Posted on:

Rate this post
0 useful
not useful
Hareesh M. wrote:


> if (a and (not b) and c = '1') then
                        -------
                              |_ type: boolean


the and operator needs operands of the same type, i.e all operands are 
boolean, or all of type std_logic.

The comparsion "c = '1'" results into type boolean; the sub-term "a and 
(not b)" into type std_logic (because a and b are of type std_logic)-> 
the rightmost "and" faces type missmatch.

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
Hareesh M. wrote:
> if(a and (not b) and c = '1') then
Try this:
 if (a and (not b) and c) then...
And this:
 if (a='1' and b='0' and c='1') then...
Then think about it.

: Edited by Moderator
Author: Markus F. (mfro)
Posted on:

Rate this post
0 useful
not useful
Lothar M. wrote:
> Hareesh M. wrote:
>> if(a and (not b) and c = '1') then
> Try this:
>  if (a and (not b) and c) then...
> And this:
>  if (a='1' and b='0' and c='1') then...


if (?? a) and (?? (not b)) and c = 1 then


> Then think about it.

Author: Hareesh Mohanan (Company: Mindteck) (hareeshp)
Posted on:

Rate this post
0 useful
not useful
thanks for your reply,

it is solved
if((a and (not b) and c) ='1' ) then
  output <= '1';
else 
 output <= '0';
end if;

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
Hareesh M. wrote:
> it is solved
> if((a and (not b) and c) ='1' ) then
I would prefer this:
if (a='1' and b='0' and c='1') then
Because there it is absolutely obvoius to see whats wanted without doing 
any logical calculations and digging around with the (not b) together 
with the ='1'...

Author: Hareesh Mohanan (Company: Mindteck) (hareeshp)
Posted on:

Rate this post
0 useful
not useful
thanks, i will change as per your suggestions.

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig