Hi, How do i access the internal signals in the top module to testbench program.The change in internal signals causes main signals to change.
Hareesh M. wrote: > How do i access the internal signals in the top module to testbench > program. Wht do you mean with "access"? Just to view the signals? Or to force them to a desired state? And most important: What simulator do you use? > The change in internal signals causes main signals to change. Indeed thats usually the desired behaviour of almost every HDL design.
Lothar M. wrote: > Hareesh M. wrote: >> How do i access the internal signals in the top module to testbench >> program. > Wht do you mean with "access"? Just to view the signals? Or to force > them to a desired state? > > And most important: What simulator do you use? > >> The change in internal signals causes main signals to change. > Indeed thats usually the desired behaviour of almost every HDL design. i want to force them to a desired state, and forcing them causes the changes in other signals too. Currently i'm using modelsim simulator.
:
Edited by User
Hareesh M. wrote: > Lothar M. wrote: >> Hareesh M. wrote: >>> How do i access the internal signals in the top module to testbench >>> program. >> Wht do you mean with "access"? Just to view the signals? Or to force >> them to a desired state? >> >> And most important: What simulator do you use? >> >>> The change in internal signals causes main signals to change. >> Indeed thats usually the desired behaviour of almost every HDL design. > > i want to force them to a desired state, and forcing them causes the > changes in other signals too. Currently i'm using modelsim simulator. i'm writing the main code and testbench for the same ////////////////////////////////////////////////////////////////////
1 | library ieee; |
2 | use ieee.std_logic_1164.all; |
3 | package vhdl_pkg is |
4 | constant HOTS_WAP: std_logic_vector(2 downto 0):= "111"; |
5 | end vhdl_pkg; |
6 | library ieee; |
7 | use ieee.std_logic_1164.all; |
8 | use ieee.numeric_std.all; |
9 | use ieee.std_logic_unsigned.all; |
10 | library work; |
11 | use work.vhdl_pkg.all; |
12 | |
13 | Entity hotswap is |
14 | port(ifc_clk: in std_logic; |
15 | BD_SEL_PLD: in std_logic:= '1'; |
16 | HS_PG00D_PLD:in std_logic:= '1'; |
17 | HS_FLT_PLD: in std_logic:= '1'; |
18 | ifc_ad0_7: inout std_logic_vector(2 downto 0); |
19 | ifc_cs3_n: in std_logic; |
20 | ifc_oe_n: in std_logic; |
21 | ifc_we_n: in std_logic; |
22 | ifc_a27_31: in std_logic_vector(2 downto 0) |
23 | );
|
24 | end hotswap; |
25 | |
26 | Architecture mpu of hotswap is |
27 | |
28 | signal ifc_dout: std_logic_vector(2 downto 0); |
29 | signal cpld_cs: std_logic; |
30 | signal cpld_oe: std_logic; |
31 | signal cpld_we: std_logic; |
32 | signal flt_reg: std_logic; |
33 | signal hotswap_pgood : std_logic; |
34 | signal bd_sel_pld_reg : std_logic; |
35 | signal pon_rst_n: std_logic; |
36 | begin
|
37 | process(ifc_clk) |
38 | begin
|
39 | if(rising_edge(ifc_clk)) then |
40 | if(pon_rst_n = '1') then |
41 | cpld_cs <= '0'; |
42 | cpld_oe <= '0'; |
43 | else
|
44 | cpld_cs <= ifc_cs3_n; |
45 | cpld_oe <= ifc_cs3_n and ifc_oe_n; |
46 | cpld_we <= ifc_cs3_n and ifc_we_n; |
47 | end if; |
48 | end if; |
49 | end process; |
50 | |
51 | process(ifc_clk) |
52 | begin
|
53 | if((cpld_cs and cpld_oe)= '1') then |
54 | case ifc_a27_31 is |
55 | when HOTS_WAP => |
56 | ifc_dout(0) <= HS_FLT_PLD; |
57 | ifc_dout(1) <= BD_SEL_PLD; |
58 | ifc_dout(2) <= HS_PG00D_PLD; |
59 | when others => |
60 | ifc_dout <= "000"; |
61 | end case; |
62 | end if; |
63 | end process; |
64 | ifc_ad0_7 (0) <= ifc_dout(0); |
65 | ifc_ad0_7 (1) <= ifc_dout(1); |
66 | ifc_ad0_7 (2) <= ifc_dout(2); |
67 | end mpu; |
///////////////////////////////////////////////////////////////////// and the testbench is
1 | library ieee; |
2 | use ieee.std_logic_1164.all; |
3 | entity hot_swap is |
4 | end entity ; |
5 | architecture hotswapping of hot_swap is |
6 | component hotswap |
7 | port( ifc_clk: in std_logic; |
8 | BD_SEL_PLD: in std_logic:= '1'; |
9 | HS_PG00D_PLD: in std_logic:= '1'; |
10 | HS_FLT_PLD: in std_logic:= '1'; |
11 | ifc_ad0_7: inout std_logic_vector(2 downto 0); |
12 | ifc_cs3_n: in std_logic; |
13 | ifc_oe_n: in std_logic; |
14 | ifc_we_n: in std_logic; |
15 | ifc_a27_31: in std_logic_vector(2 downto 0) |
16 | );
|
17 | end component; |
18 | signal ifc_clk: std_logic; |
19 | signal BD_SEL_PLD: std_logic:= '1'; |
20 | signal HS_PG00D_PLD: std_logic:= '1'; |
21 | signal HS_FLT_PLD: std_logic:= '1'; |
22 | signal ifc_ad0_7: std_logic_vector(2 downto 0); |
23 | signal ifc_cs3_n: std_logic; |
24 | signal ifc_oe_n: std_logic; |
25 | signal ifc_we_n: std_logic; |
26 | signal ifc_a27_31: std_logic_vector(2 downto 0); |
27 | constant time_tb: time:= 10 ms; |
28 | signal pon_rst_n : std_logic; |
29 | begin
|
30 | uut: hotswap port map( |
31 | |
32 | ifc_clk => ifc_clk, |
33 | BD_SEL_PLD => BD_SEL_PLD, |
34 | HS_PG00D_PLD => HS_PG00D_PLD, |
35 | HS_FLT_PLD => HS_PG00D_PLD, |
36 | ifc_cs3_n => ifc_cs3_n, |
37 | ifc_oe_n => ifc_oe_n, |
38 | ifc_we_n => ifc_oe_n, |
39 | ifc_a27_31 => ifc_a27_31); |
40 | clk: process |
41 | begin
|
42 | ifc_clk <= '1'; |
43 | wait for time_tb/2; |
44 | ifc_clk <= '0'; |
45 | wait for time_tb/2; |
46 | end process; |
47 | stimlus: process |
48 | begin
|
49 | wait for 5 ms; |
50 | pon_rst_n <= '0'; |
51 | wait for 5 ms; |
52 | pon_rst_n <= '1'; |
53 | wait for 5 ms; |
54 | ifc_a27_31 <= "111"; |
55 | wait; |
56 | end process; |
57 | end; |
:
Edited by Moderator
Usually you do NOT force an internal signal because you will not be able to do that in a real design. So apply the stimuli data (inputs) in a way you get the desired internal signals. A few words to that design: At all the simulation of this code will not match the reality due to a wrong and incomplete sensitivity list. Here in simulation it will look like the process depends on the clock, but in real life it is only a completely combinatorial process:
1 | process(ifc_clk) |
2 | begin
|
3 | if((cpld_cs and cpld_oe)= '1') then |
4 | case ifc_a27_31 is |
5 | when HOTS_WAP => |
6 | ifc_dout(0) <= HS_FLT_PLD; |
7 | ifc_dout(1) <= BD_SEL_PLD; |
8 | ifc_dout(2) <= HS_PG00D_PLD; |
9 | when others => |
10 | ifc_dout <= "000"; |
11 | end case; |
12 | end if; |
13 | end process; |
And much more worse: you implement a latch here. That is 1. not necessary, 2. not desired and 3. no good design practice. I suggest to write it without any process (using the concatenate operator '&') this way:
1 | ifc_dout <= HS_PG00D_PLD & BD_SEL_PLD & HS_FLT_PLD when |
2 | cpld_cs='1' and cpld_oe='1' and ifc_a27_31=HOTS_WAP |
3 | else "000"; |
And one word to that here:
1 | if((cpld_cs and cpld_oe)= '1') then |
Thats not a fine trick. Write it this way, it is "more usual" and better readable:
1 | if (cpld_cs='1' and cpld_oe='1') then |
If you want you can skip the parenthesis also:
1 | if cpld_cs='1' and cpld_oe='1' then |
BTW: Pls use the [vhdl] tokens around VHDL code (as described above every text edit box).
:
Edited by Moderator
thanks for your suggestion. Actually the values of HS_PG00D_PLD, BD_SEL_PLD and HS_FLT_PLD might change while execution.The width of ifc_dout is 7, for simulation i made it 3. That's why i wrote like that. And i'll change the line as per your suggestion if((cpld_cs and cpld_oe)= '1') then. and what about the testbench?
Hareesh M. wrote: > Actually the values of HS_PG00D_PLD, BD_SEL_PLD and HS_FLT_PLD might > change while execution. Then those signals must be in the sensitivity list! If you want to march on with the process, then this is the correct sensitivity list:
1 | process(HS_PG00D_PLD, BD_SEL_PLD, HS_FLT_PLD, cpld_cs, cpld_oe, ifc_a27_31) |
2 | begin
|
3 | if((cpld_cs and cpld_oe)= '1') then |
4 | case ifc_a27_31 is |
5 | when HOTS_WAP => |
6 | ifc_dout(0) <= HS_FLT_PLD; |
7 | ifc_dout(1) <= BD_SEL_PLD; |
8 | ifc_dout(2) <= HS_PG00D_PLD; |
9 | when others => |
10 | ifc_dout <= "000"; |
11 | end case; |
12 | end if; |
13 | end process; |
Hareesh M. wrote: > and what about the testbench? You already startet stimuli generation. Just go on with all the possible states:
1 | stimlus: process |
2 | begin
|
3 | wait for 5 ms; |
4 | pon_rst_n <= '0'; |
5 | wait for 5 ms; |
6 | pon_rst_n <= '1'; |
7 | wait for 5 ms; |
8 | |
9 | ifc_a27_31 <= "111"; |
10 | ifc_ad0_7 <= "ZZZ"; |
11 | BD_SEL_PLD <= '1'; |
12 | HS_PG00D_PLD <= '0'; |
13 | HS_FLT_PLD <= '0'; |
14 | ifc_cs3_n <= '0'; -- low active |
15 | ifc_oe_n <= '0'; -- low active |
16 | ifc_we_n <= '0'; -- low active |
17 | wait for 1 us; |
18 | assert ifc_ad0_7="100" report "Read not correct!" severity failure; |
19 | wait for 1 us; |
20 | |
21 | ifc_a27_31 <= "111"; |
22 | ifc_ad0_7 <= "ZZZ"; |
23 | BD_SEL_PLD <= '1'; |
24 | HS_PG00D_PLD <= '1'; |
25 | HS_FLT_PLD <= '0'; |
26 | ifc_cs3_n <= '0'; -- low active |
27 | ifc_oe_n <= '0'; -- low active |
28 | ifc_we_n <= '0'; -- low active |
29 | wait for 1 us; |
30 | assert ifc_ad0_7="110" report "Read not correct!" severity failure; |
31 | wait for 1 us; |
32 | |
33 | -- and so on
|
34 | |
35 | wait; |
36 | end process; |
BTW1: obviously all of your select signals are low active due to the _n at the end of their names. Therefore this is rubbish:
1 | cpld_cs <= ifc_cs3_n; -- low active --> high active?? |
2 | cpld_oe <= ifc_cs3_n and ifc_oe_n; -- cpld_oe is low active! |
3 | cpld_we <= ifc_cs3_n and ifc_we_n; -- cpld_we also! |
But at all this complete "control signal process" is not necessary at all. Instead it is leading to a kind of clocked bus handling. But that you will find out in simulation further on. A hint: you MUST set the inout bus to HiZ when you don't use it for output! BTW2: That looks very, very confusing to me: ifc_ad0_7: inout std_logic_vector(2 downto 0); Must it be ifc_ad2_0 instead?
Hi...i am a new user here.As per my knowledge you do NOT force an internal signal because you will not be able. To do that in a real design. So apply the stimuli data in a way you get the desired internal signals.
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