Hi, How do i access the internal signals in the top module to testbench program.The change in internal signals causes main signals to change.
Hareesh M. wrote: > How do i access the internal signals in the top module to testbench > program. Wht do you mean with "access"? Just to view the signals? Or to force them to a desired state? And most important: What simulator do you use? > The change in internal signals causes main signals to change. Indeed thats usually the desired behaviour of almost every HDL design.
Lothar M. wrote: > Hareesh M. wrote: >> How do i access the internal signals in the top module to testbench >> program. > Wht do you mean with "access"? Just to view the signals? Or to force > them to a desired state? > > And most important: What simulator do you use? > >> The change in internal signals causes main signals to change. > Indeed thats usually the desired behaviour of almost every HDL design. i want to force them to a desired state, and forcing them causes the changes in other signals too. Currently i'm using modelsim simulator.
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Edited by User
Hareesh M. wrote: > Lothar M. wrote: >> Hareesh M. wrote: >>> How do i access the internal signals in the top module to testbench >>> program. >> Wht do you mean with "access"? Just to view the signals? Or to force >> them to a desired state? >> >> And most important: What simulator do you use? >> >>> The change in internal signals causes main signals to change. >> Indeed thats usually the desired behaviour of almost every HDL design. > > i want to force them to a desired state, and forcing them causes the > changes in other signals too. Currently i'm using modelsim simulator. i'm writing the main code and testbench for the same ////////////////////////////////////////////////////////////////////
library ieee; use ieee.std_logic_1164.all; package vhdl_pkg is constant HOTS_WAP: std_logic_vector(2 downto 0):= "111"; end vhdl_pkg; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; library work; use work.vhdl_pkg.all; Entity hotswap is port(ifc_clk: in std_logic; BD_SEL_PLD: in std_logic:= '1'; HS_PG00D_PLD:in std_logic:= '1'; HS_FLT_PLD: in std_logic:= '1'; ifc_ad0_7: inout std_logic_vector(2 downto 0); ifc_cs3_n: in std_logic; ifc_oe_n: in std_logic; ifc_we_n: in std_logic; ifc_a27_31: in std_logic_vector(2 downto 0) ); end hotswap; Architecture mpu of hotswap is signal ifc_dout: std_logic_vector(2 downto 0); signal cpld_cs: std_logic; signal cpld_oe: std_logic; signal cpld_we: std_logic; signal flt_reg: std_logic; signal hotswap_pgood : std_logic; signal bd_sel_pld_reg : std_logic; signal pon_rst_n: std_logic; begin process(ifc_clk) begin if(rising_edge(ifc_clk)) then if(pon_rst_n = '1') then cpld_cs <= '0'; cpld_oe <= '0'; else cpld_cs <= ifc_cs3_n; cpld_oe <= ifc_cs3_n and ifc_oe_n; cpld_we <= ifc_cs3_n and ifc_we_n; end if; end if; end process; process(ifc_clk) begin if((cpld_cs and cpld_oe)= '1') then case ifc_a27_31 is when HOTS_WAP => ifc_dout(0) <= HS_FLT_PLD; ifc_dout(1) <= BD_SEL_PLD; ifc_dout(2) <= HS_PG00D_PLD; when others => ifc_dout <= "000"; end case; end if; end process; ifc_ad0_7 (0) <= ifc_dout(0); ifc_ad0_7 (1) <= ifc_dout(1); ifc_ad0_7 (2) <= ifc_dout(2); end mpu; |
///////////////////////////////////////////////////////////////////// and the testbench is
library ieee; use ieee.std_logic_1164.all; entity hot_swap is end entity ; architecture hotswapping of hot_swap is component hotswap port( ifc_clk: in std_logic; BD_SEL_PLD: in std_logic:= '1'; HS_PG00D_PLD: in std_logic:= '1'; HS_FLT_PLD: in std_logic:= '1'; ifc_ad0_7: inout std_logic_vector(2 downto 0); ifc_cs3_n: in std_logic; ifc_oe_n: in std_logic; ifc_we_n: in std_logic; ifc_a27_31: in std_logic_vector(2 downto 0) ); end component; signal ifc_clk: std_logic; signal BD_SEL_PLD: std_logic:= '1'; signal HS_PG00D_PLD: std_logic:= '1'; signal HS_FLT_PLD: std_logic:= '1'; signal ifc_ad0_7: std_logic_vector(2 downto 0); signal ifc_cs3_n: std_logic; signal ifc_oe_n: std_logic; signal ifc_we_n: std_logic; signal ifc_a27_31: std_logic_vector(2 downto 0); constant time_tb: time:= 10 ms; signal pon_rst_n : std_logic; begin uut: hotswap port map( ifc_clk => ifc_clk, BD_SEL_PLD => BD_SEL_PLD, HS_PG00D_PLD => HS_PG00D_PLD, HS_FLT_PLD => HS_PG00D_PLD, ifc_cs3_n => ifc_cs3_n, ifc_oe_n => ifc_oe_n, ifc_we_n => ifc_oe_n, ifc_a27_31 => ifc_a27_31); clk: process begin ifc_clk <= '1'; wait for time_tb/2; ifc_clk <= '0'; wait for time_tb/2; end process; stimlus: process begin wait for 5 ms; pon_rst_n <= '0'; wait for 5 ms; pon_rst_n <= '1'; wait for 5 ms; ifc_a27_31 <= "111"; wait; end process; end; |
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Edited by Moderator
Usually you do NOT force an internal signal because you will not be able to do that in a real design. So apply the stimuli data (inputs) in a way you get the desired internal signals. A few words to that design: At all the simulation of this code will not match the reality due to a wrong and incomplete sensitivity list. Here in simulation it will look like the process depends on the clock, but in real life it is only a completely combinatorial process:
process(ifc_clk)
begin
if((cpld_cs and cpld_oe)= '1') then
case ifc_a27_31 is
when HOTS_WAP =>
ifc_dout(0) <= HS_FLT_PLD;
ifc_dout(1) <= BD_SEL_PLD;
ifc_dout(2) <= HS_PG00D_PLD;
when others =>
ifc_dout <= "000";
end case;
end if;
end process;
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And much more worse: you implement a latch here. That is 1. not necessary, 2. not desired and 3. no good design practice. I suggest to write it without any process (using the concatenate operator '&') this way:
ifc_dout <= HS_PG00D_PLD & BD_SEL_PLD & HS_FLT_PLD when
cpld_cs='1' and cpld_oe='1' and ifc_a27_31=HOTS_WAP
else "000";
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And one word to that here:
if((cpld_cs and cpld_oe)= '1') then |
Thats not a fine trick. Write it this way, it is "more usual" and better readable:
if (cpld_cs='1' and cpld_oe='1') then |
If you want you can skip the parenthesis also:
if cpld_cs='1' and cpld_oe='1' then |
BTW: Pls use the [vhdl] tokens around VHDL code (as described above every text edit box).
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Edited by Moderator
thanks for your suggestion. Actually the values of HS_PG00D_PLD, BD_SEL_PLD and HS_FLT_PLD might change while execution.The width of ifc_dout is 7, for simulation i made it 3. That's why i wrote like that. And i'll change the line as per your suggestion if((cpld_cs and cpld_oe)= '1') then. and what about the testbench?
Hareesh M. wrote: > Actually the values of HS_PG00D_PLD, BD_SEL_PLD and HS_FLT_PLD might > change while execution. Then those signals must be in the sensitivity list! If you want to march on with the process, then this is the correct sensitivity list:
process(HS_PG00D_PLD, BD_SEL_PLD, HS_FLT_PLD, cpld_cs, cpld_oe, ifc_a27_31)
begin
if((cpld_cs and cpld_oe)= '1') then
case ifc_a27_31 is
when HOTS_WAP =>
ifc_dout(0) <= HS_FLT_PLD;
ifc_dout(1) <= BD_SEL_PLD;
ifc_dout(2) <= HS_PG00D_PLD;
when others =>
ifc_dout <= "000";
end case;
end if;
end process;
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Hareesh M. wrote: > and what about the testbench? You already startet stimuli generation. Just go on with all the possible states:
stimlus: process begin wait for 5 ms; pon_rst_n <= '0'; wait for 5 ms; pon_rst_n <= '1'; wait for 5 ms; ifc_a27_31 <= "111"; ifc_ad0_7 <= "ZZZ"; BD_SEL_PLD <= '1'; HS_PG00D_PLD <= '0'; HS_FLT_PLD <= '0'; ifc_cs3_n <= '0'; -- low active ifc_oe_n <= '0'; -- low active ifc_we_n <= '0'; -- low active wait for 1 us; assert ifc_ad0_7="100" report "Read not correct!" severity failure; wait for 1 us; ifc_a27_31 <= "111"; ifc_ad0_7 <= "ZZZ"; BD_SEL_PLD <= '1'; HS_PG00D_PLD <= '1'; HS_FLT_PLD <= '0'; ifc_cs3_n <= '0'; -- low active ifc_oe_n <= '0'; -- low active ifc_we_n <= '0'; -- low active wait for 1 us; assert ifc_ad0_7="110" report "Read not correct!" severity failure; wait for 1 us; -- and so on wait; end process; |
BTW1: obviously all of your select signals are low active due to the _n at the end of their names. Therefore this is rubbish:
cpld_cs <= ifc_cs3_n; -- low active --> high active??
cpld_oe <= ifc_cs3_n and ifc_oe_n; -- cpld_oe is low active!
cpld_we <= ifc_cs3_n and ifc_we_n; -- cpld_we also!
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But at all this complete "control signal process" is not necessary at all. Instead it is leading to a kind of clocked bus handling. But that you will find out in simulation further on. A hint: you MUST set the inout bus to HiZ when you don't use it for output! BTW2: That looks very, very confusing to me: ifc_ad0_7: inout std_logic_vector(2 downto 0); Must it be ifc_ad2_0 instead?
Hi...i am a new user here.As per my knowledge you do NOT force an internal signal because you will not be able. To do that in a real design. So apply the stimuli data in a way you get the desired internal signals.
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