Hi i have written a vhdl code along with the testbench..when i simulate 
it in the modelSim i don't get an expected result

The VHDL Code is given below

 Library ieee;
    use ieee.std_logic_1164.all;
    entity PowerSeq is
        port(fpga_clk: in std_logic;
                Enable_Bias_1V, Enable_3V3, Enable_1P5V, Enable_1V: out 
std_logic;
                PG_3V3: in std_logic);
    end PowerSeq;

    architecture MPU_PowerSeq of PowerSeq is

        signal pon_state: integer:= 0;
    begin

        process(fpga_clk)
        begin
            if(rising_edge(fpga_clk)) then

                if(pon_state = 0) then
                    Enable_3V3 <= '1';
                    Enable_1P5V <= '1';
                    Enable_1V <= '0';
                    Enable_Bias_1V <= '1';
                    pon_state <= 1;
                end if;
                    if(pon_state = 1) then
                        if(PG_3V3 = '1') then
                            Enable_1V <= '1';
                        end if;
                    end if;

                end if;
            end process;
    end MPU_PowerSeq;

------------------------------------------------------------------------ 
------------------------------------------------------------------------ 
------

 and the Test bench is also given below

  library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use ieee.std_logic_unsigned.all;
 entity PowerSeq is
 end PowerSeq;

 architecture MPU_PowerSeq of PowerSeq is

 component Sequence is
    port(fpga_clk : in std_logic;
        Reset: in std_logic;
             Enable_Bias_1V, Enable_3V3, Enable_1P5V, Enable_1V: out 
std_logic;

         PG_3V3: in std_logic);
    end component;

 signal  Reset: std_logic:= '0';
 signal  fpga_clk : std_logic:= '0';
 signal  Enable_Bias_1V: std_logic:= '0';
 signal  Enable_3V3: std_logic:= '0';
 signal  Enable_1P5V: std_logic:= '0';
 signal  Enable_1V: std_logic:= '0';
 signal  pon_state: integer:= 0;
 signal PG_3V3: std_logic:= '0';
 constant tb_time: time:= 15.5 ns;

 begin
 uut: sequence port map(
    Reset => Reset,
    fpga_clk => fpga_clk,
    Enable_Bias_1V => Enable_Bias_1V,
    Enable_3V3 => Enable_3V3,
    Enable_1P5V => Enable_1P5V,
    Enable_1V => Enable_1V,
    PG_3V3 => PG_3V3
    );

 stimlus: process
 begin
    fpga_clk <= '0' after tb_time, '1' after 2 * tb_time;
    wait for 2 * tb_time;
 end process;

 tb: process
 begin
  wait for 50 ns ;
  Reset <= '0';
  Enable_3V3 <= '0';
  Enable_3V3 <= '0';
  Enable_1V <= '0';
  wait for 50 ns;
  Reset <= '1';
  wait for 1 us;
  end process;

end;