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Author: Hareesh Mohanan (Company: Mindteck) (hareeshp)
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Hi i have written a vhdl code along with the testbench..when i simulate 
it in the modelSim i don't get an expected result

The VHDL Code is given below

 Library ieee;
    use ieee.std_logic_1164.all;
    entity PowerSeq is
        port(fpga_clk: in std_logic;
                Enable_Bias_1V, Enable_3V3, Enable_1P5V, Enable_1V: out 
std_logic;
                PG_3V3: in std_logic);
    end PowerSeq;

    architecture MPU_PowerSeq of PowerSeq is

        signal pon_state: integer:= 0;
    begin

        process(fpga_clk)
        begin
            if(rising_edge(fpga_clk)) then

                if(pon_state = 0) then
                    Enable_3V3 <= '1';
                    Enable_1P5V <= '1';
                    Enable_1V <= '0';
                    Enable_Bias_1V <= '1';
                    pon_state <= 1;
                end if;
                    if(pon_state = 1) then
                        if(PG_3V3 = '1') then
                            Enable_1V <= '1';
                        end if;
                    end if;

                end if;
            end process;
    end MPU_PowerSeq;

------------------------------------------------------------------------ 
------------------------------------------------------------------------ 
------

 and the Test bench is also given below

  library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use ieee.std_logic_unsigned.all;
 entity PowerSeq is
 end PowerSeq;

 architecture MPU_PowerSeq of PowerSeq is

 component Sequence is
    port(fpga_clk : in std_logic;
        Reset: in std_logic;
             Enable_Bias_1V, Enable_3V3, Enable_1P5V, Enable_1V: out 
std_logic;

         PG_3V3: in std_logic);
    end component;

 signal  Reset: std_logic:= '0';
 signal  fpga_clk : std_logic:= '0';
 signal  Enable_Bias_1V: std_logic:= '0';
 signal  Enable_3V3: std_logic:= '0';
 signal  Enable_1P5V: std_logic:= '0';
 signal  Enable_1V: std_logic:= '0';
 signal  pon_state: integer:= 0;
 signal PG_3V3: std_logic:= '0';
 constant tb_time: time:= 15.5 ns;

 begin
 uut: sequence port map(
    Reset => Reset,
    fpga_clk => fpga_clk,
    Enable_Bias_1V => Enable_Bias_1V,
    Enable_3V3 => Enable_3V3,
    Enable_1P5V => Enable_1P5V,
    Enable_1V => Enable_1V,
    PG_3V3 => PG_3V3
    );

 stimlus: process
 begin
    fpga_clk <= '0' after tb_time, '1' after 2 * tb_time;
    wait for 2 * tb_time;
 end process;

 tb: process
 begin
  wait for 50 ns ;
  Reset <= '0';
  Enable_3V3 <= '0';
  Enable_3V3 <= '0';
  Enable_1V <= '0';
  wait for 50 ns;
  Reset <= '1';
  wait for 1 us;
  end process;

end;

Author: Erik (Guest)
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1) What do you expect?
2) I assume this code is not to be synthesized
3) 
https://stackoverflow.com/questions/17904514/vhdl-...

Erik

Author: Hareesh Mohanan (Company: Mindteck) (hareeshp)
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thanks for your reply
 but what things should i change in testbench to make it synthesizable?

Author: guest (Guest)
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Nothing. Testbench has nothing todo with synthesiser.

Again, what is not working in your simulation?


maybe you are fooled by your resets etc?
tb: process
 begin
  wait for 50 ns ;
  Reset <= '0';
  Enable_3V3 <= '0';
  Enable_3V3 <= '0';
  Enable_1V <= '0';
  wait for 50 ns;
  Reset <= '1';
  wait for 1 us;
  end process;




tb: process
 begin
  wait for 50 ns ;
  Reset <= '0';
  Enable_3V3 <= '0';
  Enable_3V3 <= '0';
  Enable_1V <= '0';
  wait for 50 ns;
  Reset <= '1';

  wait; -- STOP THIS PROCESS HERE?


  end process;



Author: Hareesh Mohanan (Company: Mindteck) (hareeshp)
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I have changed the above testbench.


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity PowerSeq is
end PowerSeq;
architecture MPU_PowerSeq of PowerSeq is
component Sequence is
  port(fpga_clk      : in std_logic;
       Reset         : in std_logic;
       Enable_Bias_1V, Enable_3V3, Enable_1P5V, Enable_1V: out 
std_logic;
       PG_3V3        : in std_logic
       );
  end component;

    signal   Reset          : std_logic:= '0';
    signal   fpga_clk       : std_logic:= '0';
    signal   Enable_Bias_1V : std_logic:= '0';
    signal   Enable_3V3     : std_logic:= '0';
    signal   Enable_1P5V    : std_logic:= '0';
    signal   Enable_1V      : std_logic:= '0';
    signal   pon_state      : integer:= 0;
    signal   PG_3V3         : std_logic:= '0';
    constant tb_time        : time:= 1 ns;
begin

uut: sequence port map(
  Reset => Reset,
  fpga_clk => fpga_clk,
  Enable_Bias_1V => Enable_Bias_1V,
  Enable_3V3 => Enable_3V3,
  Enable_1P5V => Enable_1P5V,
  Enable_1V => Enable_1V,
  PG_3V3 => PG_3V3
  );

stimlus: process
begin
  fpga_clk <= '0' after tb_time, '1' after  2 * tb_time;
  wait for 2 * tb_time;
end process;

tb: process
    begin
    wait for 5 ns ;
    Reset <= '0';
    Enable_Bias_1V <= '1';
    Enable_3V3 <= '1';
    Enable_1P5V <= '1';
    wait for 5 ns;
    if(pon_state = 0) then
    Enable_Bias_1V <= '1';
    Enable_3V3 <= '1';
    Enable_1P5V <= '1';
    pon_state <= 1;
    end if;
    if(pon_state = 1) then
    PG_3V3 <= '1';
    Enable_1v <= '1';
    end if;
    -- wait for 5 ns;
    --Reset <= '1';
    end process;

end;

Author: Duke Scarring (Guest)
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Attached files:

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$ vlib work

$ vcom sequencer.vhd
Model Technology ModelSim SE-64 vcom 10.3d Compiler 2014.10 Oct  7 2014
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity PowerSeq
-- Compiling architecture MPU_PowerSeq of PowerSeq
Errors: 0, Warnings: 0

$ vcom sequencer_tb.vhd
Model Technology ModelSim SE-64 vcom 10.3d Compiler 2014.10 Oct  7 2014
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Loading package std_logic_arith
-- Loading package STD_LOGIC_UNSIGNED
-- Compiling entity PowerSeq
-- Compiling architecture MPU_PowerSeq of PowerSeq
###### sequencer_tb.vhd(8): component Sequence is
** Error: sequencer_tb.vhd(8): near "Sequence": expecting IDENTIFIER
Errors: 1, Warnings: 0

After fixing some identifiers errors.
Than I had to fix mismatched component/entity description and - maybe 
this is the important thing - add additional delay after "if(pon_state = 
0) then ... end if;" in your stimulus generation.
Take a look again for the concept of signals in VHDL.

See simulation results in the picture. I also attach the modified 
testbench.

Duke

Author: world's best FPGA-Pongo (Guest)
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I am always impressed that people spend time on analyzizng other 
people's code to find the syntax issues. Shouldn't it be a task to learn 
to do that by one self?

BTW:  Duke, you seem to be using and old MOdelSIM with data 2014.

>"Model Technology ModelSim SE-64 vcom 10.3d Compiler 2014.10 Oct  7 2014"

Why is this?
Are you using an old dongle, too? :D :D :D

Author: Duke Scarring (Guest)
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world's best FPGA-Pongo wrote:
Syntax errors are easy to remedy.

> Why is this?
No time for update :-)
(And I don't need the new features yet.)

Duke

Author: Hareesh Mohanan (Company: Mindteck) (hareeshp)
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Hi Duke,
Actually i have a doubt about the code you have edited. can we use 'if' 
statement inside a uut process?

Author: Duke Scarring (Guest)
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Hareesh M. wrote:
> can we use 'if'
> statement inside a uut process?
Yes of course.

See LRM (p. 125):
https://edg.uchicago.edu/~tang/VHDLref.pdf

Duke

Author: Hareesh Mohanan (Company: Mindteck) (hareeshp)
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thanks for your reply..I will go through this pdf.

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