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Forum: FPGA, VHDL & Verilog MAC architecture (adder / accumulator) 16 bits


von Pollyana (Guest)


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Hello! I need to do a VHDL project of a 16 bit MAC (Adder / Accumulator) 
architecture with a structure using RAM, ROM, Multiplexer and Counter. 
Does anyone have any idea how this structure would look?
thanks.

von Strubi (Guest)


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This is meant to be homework, I would bet. Hint: the 'M' in MAC stands 
for multiplicator.

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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Pollyana wrote:
> a VHDL project of a 16 bit MAC (Adder / Accumulator) architecture with a
> structure using RAM, ROM, Multiplexer and Counter
Only those?
Or can you use a multiplier and an adder also?

von Pollyana (Guest)


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I can use others as long as I use those too

von Pollyana (Guest)


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Lothar M. wrote:
> Pollyana wrote:
>> a VHDL project of a 16 bit MAC (Adder / Accumulator) architecture with a
>> structure using RAM, ROM, Multiplexer and Counter
> Only those?
> Or can you use a multiplier and an adder also?

I can use others as long as I use those too

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