EmbDev.net

Forum: FPGA, VHDL & Verilog MAC architecture (adder / accumulator) 16 bits


Author: Pollyana (Guest)
Posted on:

Rate this post
0 useful
not useful
Hello! I need to do a VHDL project of a 16 bit MAC (Adder / Accumulator) 
architecture with a structure using RAM, ROM, Multiplexer and Counter. 
Does anyone have any idea how this structure would look?
thanks.

Author: Strubi (Guest)
Posted on:

Rate this post
0 useful
not useful
This is meant to be homework, I would bet. Hint: the 'M' in MAC stands 
for multiplicator.

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
Pollyana wrote:
> a VHDL project of a 16 bit MAC (Adder / Accumulator) architecture with a
> structure using RAM, ROM, Multiplexer and Counter
Only those?
Or can you use a multiplier and an adder also?

Author: Pollyana (Guest)
Posted on:

Rate this post
0 useful
not useful
I can use others as long as I use those too

Author: Pollyana (Guest)
Posted on:

Rate this post
0 useful
not useful
Lothar M. wrote:
> Pollyana wrote:
>> a VHDL project of a 16 bit MAC (Adder / Accumulator) architecture with a
>> structure using RAM, ROM, Multiplexer and Counter
> Only those?
> Or can you use a multiplier and an adder also?

I can use others as long as I use those too

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig