EmbDev.net

Forum: FPGA, VHDL & Verilog VHDL coding Register assignment


VHDL coding Register assignment
von Hareesh M. (Company: Mindteck) (hareeshp)

Rate this post
• ▲ useful
▼ not useful 
Hi,
How can i transfer 20 zeros to a register having 20 bit memory in vhdl.

   a <= "00000000000000000000";
is there any short code for the above assignment?

: Edited by User
Report post Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote
Re: VHDL coding Register assignment
von ui (Guest)

Rate this post
• ▲ useful
▼ not useful 
1
a <= (others => '0');

Report post Edit Delete Quote selected text Reply Reply with quote
Re: VHDL coding Register assignment
von Hareesh M. (Company: Mindteck) (hareeshp)

Rate this post
• ▲ useful
▼ not useful 
ui wrote:
> a <= (others => '0');

thanks for your reply...and i have one more doubt.
how can we assign a register with decimal value, like we are assigning 
in verilog
 if(req_cop_trst_cnt >= 20'd131072) // verilog

Report post Edit Delete Quote selected text Reply Reply with quote
Re: VHDL coding Register assignment
von ui (Guest)

Rate this post
• ▲ useful
▼ not useful 
You cannot like in verilog. You need to do it explicity. For this you 
need to cast your integer first to unsigned or signed and then to 
std_logic_vector.
see http://www.bitweenie.com/listings/vhdl-type-conversion/

Report post Edit Delete Quote selected text Reply Reply with quote
Watch this topic | Disable multi-page view
Please log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
No account? Register here.