# Forum: DSP CIC Decimation by factor 100000?

 Author: Marcel D. (diablokiller999) Posted on: 2017-07-21 11:41

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Hi guys!
I need to filter some samples that come in at 10MHz down to 100Hz, 1KHz
and 10KHz. I thought using a CIC filter with a FIR afterwards to cut out
aliased spectral components should be a good idea to do this.
After all, everything should be implemented into a FPGA. But after some
simulation in Scilab, this seems like a complex job. My -3dB frequency
is around 3000Hz if I'm not doing sth. wrong in my Scilab program.
Decimation Rate is 32, Waiting Cycles is also 32 while the number of
stages is 3.

Should I try some more calculations and implement it the way I planned
or is there a better solution to my needs I don't see right now?

: Edited by User
 Author: Gerald (Guest) Posted on: 2017-07-22 23:24

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Hi,

CIC filter is a good way.
I would try to decimate with ~3 concatenated CIC Filter, each with a FIR
CIC-compensation filter.
the filter as vhdl.

 Author: signal processing engineer (Guest) Posted on: 2017-07-22 23:55

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this is the most crappy idea thinkable to stack several CICs. This all
can be done witin one step if done correctly. Also stacking FIRs is not
efficient and can be done in one step with appropriate numbers of TAPs.

 Author: Marcel D. (diablokiller999) Posted on: 2017-07-24 07:22

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So was my attempt with decimation down to 1KHz and a FIR to 100Hz a good
approach? I have a Scilab-Program to determine the attenuation and want
-3dB frequency to be at 1000Hz, but it crashes everytime I get below
5KHz ^^
Has anyone a better solution? Maybe for Octave?

 clear all; z=poly(0,'z'); R=256; // CIC divider Ratio M=3; // CIC stages N=1;// CIC delay stages Scale=0; num=(z**(R*N)-1)**M;// Based of 1-z**(-R*D) den=(z**(R*N)-z**((R*N)-1))**M;// Based of 1-z**-1 Pd=syslin('d',num,den); //Frequency Response fsample=10e6/2**Scale;// Input sample frequency fmin = 0.00001;// min frequency fmax = 1; //max. Frequency (normalized), Nyquist frequency at 0.5 //Pd=Pd**M; Pdnom= (Pd+0.001)/(R*N)**M;//normalized transfer function //scf(2); bode(Pdnom,fmin,fmax); [frq1,rep]=repfreq(Pdnom,fmin,fmax,0.0001);//Frequency response in 0.001 steps OutdB=10*log(abs(rep));//Amplitude in dB frq_plot=frq1.*fsample; scf(3); //clf; plot("nl",frq_plot, OutdB,'black'); xlabel('Frequency in Hz'); ylabel('Magnitude in dB'); xgrid(2); title('Frequency Response of the first and the second CIC decimation Filter ')

 Author: Marcel D. (diablokiller999) Posted on: 2017-07-24 09:25

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Tried a bit Octave, found some small programs to deal with. By building
a CIC with 2048 decimation, 3 stages and 1 delay time I get a graph that
tells me my -3dB frequency is at 1272Hz. Afterwards I designed a FIR
with hamming window/1272Hz sampling rate and get around 104Hz @ -3dB and
very steep attenuation. Does this look like a good design choice, do the
values even make sense or did I screw up somewhere? ^^
Yeah, I'm fairly new to filters indeed...

: Edited by User
 Author: Markus W. (elektrowagi78) Posted on: 2017-10-19 18:05

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where is the problem using a cic with more then ratio 2048 ?

What is the target for a) 10MHz filtering, ... b) ... c) 100 kHz?

Which shall be the edge freuency?

 Author: Martin O. (Guest) Posted on: 2017-11-11 13:22

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If you decimate by a high ratio the number of bits needed in the CIC
grow,
especiially with higher order CIC stages. Therefore it might be better
to cascade CIC stages.

 Author: Derrick Corea (Guest) Posted on: 2017-11-24 11:42

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Thanks for the above code.

 Author: Markus W. (elektrowagi78) Posted on: 2017-11-26 21:27

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Martin O. wrote:
> If you decimate by a high ratio the number of bits needed in the CIC
> grow,
> especiially with higher order CIC stages. Therefore it might be better

you are not telling us, that some tiny little bits will increas an FPGA
design much more, than tripeling it by using it three times?

An FPGA decimation with CIC is notinh else than a counter and a sampler
for the counter and some adds and sub. More bits will increase the
counter size.

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