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Forum: FPGA, VHDL & Verilog constrain implementation


Author: Sophie Ttazeaee (Company: zeazeazea) (totor)
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Hello every one,
Here is a part of my code:
      when MC_BIT_AND =>        alu_out <= alu_in1 and alu_in2;
      when MC_BIT_OR =>         alu_out <= alu_in1 or  alu_in2;
      when MC_BIT_XOR =>        alu_out <= alu_in1 xor alu_in2;
      when MC_BIT_ASL =>        alu_out <= alu_in1(7 downto 0) & "0";
      when MC_BIT_LSR =>        alu_out <= alu_in1(0) & "0" & alu_in1(7 downto 1);
      when MC_BIT_ROL =>        alu_out <= alu_in1(7 downto 0) & c_flag;
      when MC_BIT_ROR =>        alu_out <= alu_in1(0) & c_flag & alu_in1(7 downto 1);
      when others =>            alu_out <= alu_in1;

I have to separate physicly all "when" banches of the code (it would be 
a bit complex to explain why). I looked at xilinx constrains guide and I 
have seen "keep hierarchy" constrain but it seems to work only for 
entities.
Does anyone get an idea of what to do?
Thank you in advance

Author: Lothar Miller (lkmiller) (Moderator)
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Sophie T. wrote:
> Does anyone get an idea of what to do?
I didn't get the problem at all.

> I have to separate physicly all "when" banches of the code
> (it would be a bit complex to explain why).
It would be very interesting why.
Especially why a obvious beginner needs such an advanced procedure...

> I have to separate physicly all "when" banches of the code
You cannot do any "physics" like you want in VHDL code.
So, whats the actual problem?

Author: Sophie Ttazeaee (Company: zeazeazea) (totor)
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The reason why I need to use a such advanced procedure is that I'm 
studiing coupling effect on low distance implementation. Even if you are 
right, why are you saying I'm a beginner?

You says that we cannot do "physics" in VHDL nevertheless we can input 
"physical constrains" according to xilinx documentation so I don't 
understand.

"I didn't get the problem at all." , "So, whats the actual problem?"

I will do 2 measures and I need 2 different implementation, one with a 
low distance between my all the posibilities of the "when" and one with 
more important distance.
I know that I will have the same results in terms of input and output 
but that's not the point, I measure power consumption.

Author: Lothar Miller (lkmiller) (Moderator)
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Sophie T. wrote:
> Even if you are right, why are you saying I'm a beginner?
As you expect to be able to control such behaviour with a HDL 
description. If you want to dig down deep in hardware, then you must 
access the floorplanner

> I will do 2 measures and I need 2 different implementation, one with a
> low distance between my all the posibilities of the "when" and one with
> more important distance.
As I said: there is no "distance" with these "when", because there is no 
"when" inside the FPGA. You will only find 4 or 6-input LUT which will 
incoorporate the functionality you describe. The most important desire 
of the toolchain is to keep the whole logic as compact and fast as 
possible.

The only thing you can do is to separate those LUT involved in the logic 
to get long distance lines between them. But there is no formula like "1 
when = 1 LUT"...

: Edited by Moderator
Author: Klakx (Guest)
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put every Statement in a seperate module like y <= alu_in1 and alu_in2 
and y <= alu_in1 or alu_in2, and so on.

In your upper state module you link only the Outputs.
when MC_BIT_AND =>        alu_out <= y1;
when MC_BIT_OR =>         alu_out <= y2;

in your designflow you should floorplan your subcomponents afterwards.

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