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Forum: FPGA, VHDL & Verilog RTL technique about "for" combine


Author: murakami (Guest)
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I would like to know how to combine below two.

generate
    for (i=0; i<10; i=i+1) begin
        a <= b;
    end
    for (i=20; i<30; i=i+1) begin
        a <= b;
    end
endgenerate


I did like (i=0||i=20; i<10||(i>=20 && i<30); i=i+1)
but failed because I seemed not to able to put two initial.

Could somebody help?

Author: Lothar Miller (lkmiller) (Moderator)
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murakami wrote:
> I did like (i=0||i=20; i<10||(i>=20 && i<30); i=i+1)
Why did you try that? Do you know any VHDL book using any of those 
operators in that way? Is && a VHDL operator at all?

> but failed
Yes of course. You type a random combination of characters in one line 
and expect a tool to understand what you want?
Usually it goes the other way round: you read a manual for a language 
and use it in a manner the syntax and the behavior is defined.

And now let's try it once more: what do you want to do? Assign B to A 
twenty times?

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