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Verilog with FSM
von Rytis (Guest)

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Hey guys, i need help. test bench file don't working :(((((((
this is verilog module


module kursinis(clk, SB, O35, O4, CB, LED2ON, LED1, LED3, LED2BLINK, 
state);
  // SB-START_BUTTON, O3-OVER_3V, O4-OVER_4V, CB- CONTROL_BUTTON
input clk, SB, O35, O4, CB;
output LED2ON, LED1, LED3, LED2BLINK;
output [2:0]state;

//busenos DB-dead battery, LB- low battery, FB- full battery, 
C1-calibrated1, C2-calibtrated2
parameter  OFF= 3'b001,  DB= 3'b010,  LB= 3'b011,  FB= 3'b100,  C1= 
3'b101, C2=3'b110;
//esamos busenos registras ir kitos busenos signalas
reg [2:0] state_reg, state_next;
reg LED2ON, LED1, LED3, LED2BLINK;
assign state = state_reg;
// busenu registro perrasymas
always @(posedge clk)
begin
  state_reg <= state_next;
end
// kitos busenos skaiciavimas
always @(state_reg, clk, SB, O35, O4, CB)
begin
  case(state_reg)
        OFF : if (SB == 1'b1) begin
                state_next <= DB;
                LED2ON <= 1'b1;
              end
              else begin
                state_next <= OFF;
              end

         DB : if (SB == 1'b0) begin
                state_next <= OFF;
                LED2ON <= 1'b0;
              end else if (O35 == 1'b1) begin
                state_next <= LB;
                LED2ON <= 1'b0;
                LED2BLINK <= 1'b1;
              end
              else begin
                state_next <= DB;
              end

         LB : if (SB == 1'b0) begin
                state_next <= OFF;
                LED2BLINK <= 1'b0;
              end else if (O4 == 1'b1) begin
                state_next <= FB;
                LED2BLINK <= 1'b0;
                LED1 <= 1'b1;
              end else if (O35 == 0'b1) begin
                state_next <= DB;
                LED2BLINK <= 1'b0;
                LED2ON <= 1'b1;
              end else if (CB == 1'b1) begin
                state_next <= C1;
                LED3 <= 1'b1;
              end
              else begin
                state_next <=LB;
              end

         FB : if (SB == 1'b0) begin
                state_next <= OFF;
                LED1 <= 1'b0;
              end else if (O4 == 1'b0) begin
                state_next <= LB;
                LED2BLINK <= 1'b1;
                LED1 <= 1'b0;
              end else if (CB == 1'b1) begin
                state_next <= C2;
                LED3 <= 1'b1;
              end
              else begin
                state_next <=FB;
              end

         C1 : if (SB == 1'b0) begin
                state_next <= OFF;
                LED3 <= 1'b0;
                LED2BLINK <= 1'b0;
              end else if (CB == 1'b0) begin
                state_next <= LB;
                LED3 <= 1'b0;
              end else if (O35 == 1'b0) begin
                state_next <= DB;
                LED3 <= 1'b0;
                LED2ON <= 1'b1;
                LED2BLINK <= 1'b0;
              end
              else begin
                state_next <= C1;
              end

         C2 : if (SB == 1'b0) begin
                state_next <= OFF;
                LED3 <= 1'b0;
                LED1 <= 1'b0;
              end else if (CB == 1'b0) begin
                state_next <= FB;
                LED3 <= 1'b0;
              end else if (O4 == 1'b0) begin
                state_next <= C1;
                LED1 <= 1'b0;
                LED2BLINK <= 1'b1;
              end
              else begin
                state_next <= C2;
              end
        endcase
      end
  endmodule

////////////////////////////////////////////////////////////////
and this is test bench file
module kursinis_tb;
  reg clk, SB, O35, O4, CB;
  output LED2ON, LED1, LED3, LED2BLINK;
  output [2:0]state;

  kursinis pirmas(
  .clk (clk),
  .SB (SB),
  .O35 (O35),
  .O4 (O4),
  .CB (CB),
  .LED2ON (LED2ON),
  .LED1 (LED1),
  .LED3 (LED3),
  .LED2BLINK (LED2BLINK),
  .state (state)
  );

  initial
    begin
        clk =0;
        SB=0;
        O35=0;
        O4=0;
        CB=0;
  end

always
#50 clk = !clk;
initial
begin
  #100 SB=1;
  #100 O35=1;
  #5000 $stop;
end
endmodule

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Re: Verilog with FSM
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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Rytis wrote:
> test bench file don't working :(((((((
WHAT is not working? WHAT do you expect? And WHAT do you get instead?

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Re: Verilog with FSM
von sharon Maxwell (Guest)

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/====================================================
  2 // This is FSM demo program using single always
  3 // for both seq and combo logic
  4 // Design Name : fsm_using_single_always
  5 // File Name   : fsm_using_single_always.v
  6 //=====================================================
  7 module fsm_using_single_always (
  8 clock      , // clock
  9 reset      , // Active high, syn reset
 10 req_0      , // Request 0
 11 req_1      , // Request 1
 12 gnt_0      , // Grant 0
 13 gnt_1
 14 );
 15 //=============Input Ports=============================
 16 input   clock,reset,req_0,req_1;
 17  //=============Output Ports===========================
 18 output  gnt_0,gnt_1;
 19 //=============Input ports Data Type===================
 20 wire    clock,reset,req_0,req_1;
 21 //=============Output Ports Data Type==================
 22 reg     gnt_0,gnt_1;
 23 //=============Internal Constants======================
 24 parameter SIZE = 3           ;
 25 parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ;
 26 //=============Internal Variables======================
 27 reg   [SIZE-1:0]          state        ;// Seq part of the FSM
 28 reg   [SIZE-1:0]          next_state   ;// combo part of FSM
 29 //==========Code startes Here==========================
 30 always @ (posedge clock)
 31 begin : FSM
 32 if (reset == 1'b1) begin
 33   state <=  #1  IDLE;
 34   gnt_0 <= 0;
 35   gnt_1 <= 0;
 36 end else
 37  case(state)
 38    IDLE : if (req_0 == 1'b1) begin
 39                 state <=  #1  GNT0;
 40                 gnt_0 <= 1;
 41               end else if (req_1 == 1'b1) begin
 42                 gnt_1 <= 1;
 43                 state <=  #1  GNT1;
 44               end else begin
 45                 state <=  #1  IDLE;
 46               end
 47    GNT0 : if (req_0 == 1'b1) begin
 48                 state <=  #1  GNT0;
 49               end else begin
 50                 gnt_0 <= 0;
 51                 state <=  #1  IDLE;
 52               end
 53    GNT1 : if (req_1 == 1'b1) begin
 54                 state <=  #1  GNT1;
 55               end else begin
 56                 gnt_1 <= 0;
 57                 state <=  #1  IDLE;
 58               end
 59    default : state <=  #1  IDLE;
 60 endcase
 61 end
 62
 63 endmodule // End of Module arbiter

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