Simple question about a case statement

hello, I'm a newbie in verilog and I'm trying to make a case statement 
that when I introduce a data, it will give me another data depending on 
the one introduced

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module cases(data_in, data_out2);

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parameter A =  8'h1C;

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parameter B =   8'h32;

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parameter C =   8'h21;

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input [7:0] data_in;

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output reg [7:0] data_out2;

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always@(data_in)

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begin

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  case(data_in)

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  A: data_out2 = 8'h41;

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  B: data_out2 = 8'h42;

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  C: data_out2 = 8'h43;

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  endcase

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end

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endmodule

This is what I did, but so far it doesn't do anything, it just gives an 
output without introducing data, it is displayed in a 7 segment display 
and, it just gives the number 42.

Can anyone help me telling me the error?