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Forum: FPGA, VHDL & Verilog Simple question about a case statement


Author: Luis G. (blasterfire)
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hello, I'm a newbie in verilog and I'm trying to make a case statement 
that when I introduce a data, it will give me another data depending on 
the one introduced
module cases(data_in, data_out2);

parameter A =  8'h1C;
parameter B =   8'h32;
parameter C =   8'h21;

input [7:0] data_in;
output reg [7:0] data_out2;

always@(data_in)
begin
  case(data_in)
  A: data_out2 = 8'h41;
  B: data_out2 = 8'h42;
  C: data_out2 = 8'h43;
  endcase
end
endmodule

This is what I did, but so far it doesn't do anything, it just gives an 
output without introducing data, it is displayed in a 7 segment display 
and, it just gives the number 42.

Can anyone help me telling me the error?

: Edited by Moderator
Author: Lothar M. (lkmiller) (Moderator)
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Luis G. wrote:
> This is what I did, but so far it doesn't do anything
How did you test it? What toolchain? What platform?

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