If or else if? Which is faster?

Guest #4985100 
In a Verilog/VHDL design, Say that you have n (any number) completely 
mutually exclusive events i.e. the events never occur simultaneously and 
there is hence no priority associated with any event.In such a scenario, 
what would be faster?


if (condition 1)
if (condition 2)
if (condition 3)
.
.
.
.
.
--------   OR  ----------
if (condition 1)
else if (condition 2)
else if (condition 3)
.
.
.
.
.

In my opinion, I think the simple ifs would work out better since the 
priority doesn't have to be checked and would infer less hardware.In C 
or MATLAB, the opposite may be true because if condition 1 turns out to 
be true then all remaining conditions can be skipped by using else if. 
My question is specific to VERILOG/VHDL.
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Guest 
its not so much a question of speed, but the fact that multiple 
consecutive if-statements are another contruct than an "if .. else if" 
block.

consecutive if's are executed each one by one, while an "if .. else if" 
block is finished if one condition is met.
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Guest 
I get that.It is not a matter of speed, but what would infer simpler 
hardware? I guess by speed I meant fewer gates and less 
hardware/combinational logic.
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Guest 
Code:

1
library IEEE;

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use IEEE.STD_LOGIC_1164.ALL;

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entity test is Port(

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  in_a: in std_logic_vector(3 downto 0);

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  select_a: in std_logic_vector(1 downto 0);

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  out_a: out std_logic;

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  in_b: in std_logic_vector(3 downto 0);

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  select_b: in std_logic_vector(1 downto 0);

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  out_b: out std_logic);

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end test;

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architecture Behavioral of test is

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begin

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process (select_a, select_b) begin

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  if select_a = "00" then out_a <= in_a(0); end if;

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  if select_a = "01" then out_a <= in_a(1); end if;

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  if select_a = "10" then out_a <= in_a(2); end if;

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  if select_a = "11" then out_a <= in_a(3); end if;

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  if    select_b = "00" then

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    out_b <= in_b(0);

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  elsif select_b = "01" then

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    out_b <= in_b(1);

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  elsif select_b = "10" then

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    out_b <= in_b(2);

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  elsif select_b = "11" then

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    out_b <= in_b(3);

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  end if;

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end process;

33


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end Behavioral;
Attached files:
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Guest 
Thank you for your input! I plan on doing something similar in Quartus 
Prime and Xilinx ISE.
Thank you!
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