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#4985100
In a Verilog/VHDL design, Say that you have n (any number) completely mutually exclusive events i.e. the events never occur simultaneously and there is hence no priority associated with any event.In such a scenario, what would be faster? if (condition 1) if (condition 2) if (condition 3) . . . . . -------- OR ---------- if (condition 1) else if (condition 2) else if (condition 3) . . . . . In my opinion, I think the simple ifs would work out better since the priority doesn't have to be checked and would infer less hardware.In C or MATLAB, the opposite may be true because if condition 1 turns out to be true then all remaining conditions can be skipped by using else if. My question is specific to VERILOG/VHDL.