In a Verilog/VHDL design, Say that you have n (any number) completely mutually exclusive events i.e. the events never occur simultaneously and there is hence no priority associated with any event.In such a scenario, what would be faster? if (condition 1) if (condition 2) if (condition 3) . . . . . -------- OR ---------- if (condition 1) else if (condition 2) else if (condition 3) . . . . . In my opinion, I think the simple ifs would work out better since the priority doesn't have to be checked and would infer less hardware.In C or MATLAB, the opposite may be true because if condition 1 turns out to be true then all remaining conditions can be skipped by using else if. My question is specific to VERILOG/VHDL.

its not so much a question of speed, but the fact that multiple consecutive if-statements are another contruct than an "if .. else if"block. consecutive if's are executed each one by one, while an "if .. else if" block is finished if one condition is met.

I get that.It is not a matter of speed, but what would infer simpler hardware? I guess by speed I meant fewer gates and less hardware/combinational logic.

Test it! Write two simple Designs which are nearly identical and look at the Hardware.

Code:

1 | library IEEE; |

2 | use IEEE.STD_LOGIC_1164.ALL; |

3 | |

4 | entity test is Port( |

5 | in_a: in std_logic_vector(3 downto 0); |

6 | select_a: in std_logic_vector(1 downto 0); |

7 | out_a: out std_logic; |

8 | in_b: in std_logic_vector(3 downto 0); |

9 | select_b: in std_logic_vector(1 downto 0); |

10 | out_b: out std_logic); |

11 | end test; |

12 | |

13 | architecture Behavioral of test is |

14 | |

15 | ```
begin
``` |

16 | |

17 | process (select_a, select_b) begin |

18 | if select_a = "00" then out_a <= in_a(0); end if; |

19 | if select_a = "01" then out_a <= in_a(1); end if; |

20 | if select_a = "10" then out_a <= in_a(2); end if; |

21 | if select_a = "11" then out_a <= in_a(3); end if; |

22 | |

23 | if select_b = "00" then |

24 | out_b <= in_b(0); |

25 | elsif select_b = "01" then |

26 | out_b <= in_b(1); |

27 | elsif select_b = "10" then |

28 | out_b <= in_b(2); |

29 | elsif select_b = "11" then |

30 | out_b <= in_b(3); |

31 | end if; |

32 | end process; |

33 | |

34 | end Behavioral; |

Thank you for your input! I plan on doing something similar in Quartus Prime and Xilinx ISE. Thank you!