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Forum: FPGA, VHDL & Verilog Vivado warning for RAM component


Vivado warning for RAM component
von Tudor I. (megax)

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Hello guys..I have a pretty big project implemented and while it works 
perfectly on Active HDL, on FPGA board it works only partially.. the 
main idea is that I noticed that it doesn't read from 2 RAM components 
that I created (in the attachment I provided one of them because they 
are the same, only different informations in my_ram) and I suspect it 
has something to do with this warning that I get during synthesis: 
[Synth 8-327] inferring latch for variable 'my_ram_reg[1]' 
["C:/My_Designs/yessir/bancomat/src/RAM-PIN.vhd":25] ( and it happens 
from my_ram_reg[1] to [7] ).. what I'm trying to do is read the 
information from that array that I created and use it in a process.. for 
example, the number that I read from this RAM is used in an addition. I 
can provide more files if needed...sorry for bothering but right now I'm 
just learning VHDL

EDIT: I'm trying to link RAM component to read from it like this:
INTEROGARE: RAM2 port map (index,'1','0',"0000000000000000",suma); and 
on the displays it shows data_in value... if I modify the last bit with 
'1'.. it shows 0000000000000001

: Edited by User
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Re: Vivado warning for RAM component
von -gb- (Guest)

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process(cs,adress,data_in,we,my_ram)

You are using a process without a clock. This is fine, but the 
sensitivity list is only used in simulation.

The warning
[Synth 8-327] inferring latch for variable 'my_ram_reg[1]'
["C:/My_Designs/yessir/bancomat/src/RAM-PIN.vhd":25]
tells you, that because of no clock you get a latch (and the toolchain 
will not use BlockRAM or FFs).

So in Hardware
1
if cs='1' then

2
  data_out<="1001100110011001";

3
else

4
  if we='1' then

5
    data_out<=my_ram(to_integer(unsigned(adress)));

6
  else my_ram(to_integer(unsigned(adress)))<=data_in;

7
    data_out<="1101101011011010";

8
  end if;

9
end if;


runs parallel all the time. So if cs = '0' and we = '0' data is written 
to RAM. How did you test ist? If you know what you do this might be ok.

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Re: Vivado warning for RAM component
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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Tudor I. wrote:
> sorry for bothering but right now I'm just learning VHDL
You must distinguish between "VHDL for simulation" and "VHDL for 
synthesis". For the first one you can use almost all of the VHDL syntax 
elements.
And for the second one you must read in the synthesizers manual what 5% 
of "the VHDL language" you can use to describe hardware in a FPGA or an 
ASIC.

If you want to infer RAM, then read the according chapter in the 
synthesizers manual, and write it the very same way in your code. Then 
maybe you will get what you want: a RAM block inside the FPGA is used.

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