Hello... I'm trying to implement a design which increases a 16-bit vector on each 4 bits, depending on a selection and button which increases the respective 4-bits which are selected by the selections and im getting the following error when im trying to synthesize it: Line 21: statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition Please help me to resolve this
A clock in a FPGA is described with 'event. Have a look how others use this attribute, or read your synthesizers manual how to invoke clocked flipflops. BTW: never use a badly bouncing button as a clock source. In a FPGA design usually the one and only clock has something around 50Mhz. Use this clock to sync in the bouncing button and then and after debouncing do an edge detection on that signal. Then you have a perfect synchronous design.
Oh so basically this means that I should include my debouncing component on the button from my FPGA and the output of that should be the "button" for this component?
: Edited by User
EDIT: I tried using debouncing on that button and I get the same error...
at first you should rewrite your code like this: if clk'event and clk = '1' then case .. end case; end if;
Tudor I. wrote: > EDIT: I tried using debouncing on that button How? Debouncing simply means: check for a stable signal for e.g. 20ms. And then add an edge detection for the counting... Something like this: http://www.lothar-miller.de/s9y/archives/3-Tastenentprellung-mit-Schieberegister.html And as I said: look how others did it. Look a ten designs and do it like the majority does it. Then you are not that far away from a synthesizable result.
: Edited by Moderator