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Forum: FPGA, VHDL & Verilog Error (10349): VHDL Association List error at bin_7seg_tester.vhd(13): formal "bin" does not exist


Author: Emil (Guest)
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Hello,

I've been working on a binary to 7-segment display. Where the input is a 
binary number, that's then to be showed on the 7-segment display in HEX.
I've written code as the following two screenshots will show, and am 
presented with the errors below them:
https://gyazo.com/9c53ce6c9097be5a74da05466c1949b8
https://gyazo.com/9d1210b000f7a2bfbfa6bca96c33f289

Error (10349): VHDL Association List error at bin_7seg_tester.vhd(13): 
formal "bin" does not exist
Error (10346): VHDL error at bin_7seg_tester.vhd(12): formal port or 
parameter "SW" must have actual or default value
Error (10784): HDL error at bin_7seg_tester.vhd(6): see declaration for 
object "SW"


I have no clue why it doesn't work, any help is appreciated. Thanks!
Am using an Altera DE2 board, and writing the code in Quartus II.

Author: Lothar Miller (lkmiller) (Moderator)
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Emil wrote:
> I've written code as the following two screenshots will show
Simply copy the code here wrapped by the [vhdl] tags or attach it as a 
*.vhdl file. I will not download any spam from a dubious source...

Or at least attach those screenshot-sourcecode-snippets here in the 
forum.

: Edited by Moderator

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