Synchronization logic for DAQ IP

Lothar M. Moderator (Company: Titel) #4972385
Rate this post
• ▲ useful
▼ not useful 
Viya V. wrote:
> what is the need of synchronization logic in data acquisition IP.
Wht is your definition of DAQ?
What abstraction layer are you discussing?

If it is on gate level, then there is a need to synchronize every async 
external signal.
If it is on a higher level, there may be a need for synchronizing data 
sampling to specific time stamps or to other data channels.

> I am trying to developing a DAQ IP
> My DAQ IP is not processing any data, simply acquires samples from ADC.
What ADC? With what device? What platform, what HDL and what toolchain?
Reply Quote Edit Delete Report post
Watch this topic

Reply

Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.

Formatting
  • [c]C-Code[/c]
  • [vhdl]VHDL-Code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]
  • [[Title]] – link to an article
  • Link to another post: right-click its post ID (#8078628), copy the address, paste it into the text

More about formatting

Post long source code as an attachment, not in the text.

Your name and e-mail address

Already registered? Log in

Not shown to anyone. We send you a link; your post appears once you confirm it there.

By submitting you create a free account and accept the terms of use.