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Forum: FPGA, VHDL & Verilog Synchronization logic for DAQ IP


Author: Viya Vijayan (viyaaloth)
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Dear All,

Can anyone tell me what is the need of synchronization logic in data 
acquisition IP. Is it a mandatory feature?? . I am trying to developing 
a DAQ IP. My DAQ IP is not processing any data, simply acquires samples 
from ADC.

Regards,
Viyaaloth

Author: Lothar Miller (lkmiller) (Moderator)
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Viya V. wrote:
> what is the need of synchronization logic in data acquisition IP.
Wht is your definition of DAQ?
What abstraction layer are you discussing?

If it is on gate level, then there is a need to synchronize every async 
external signal.
If it is on a higher level, there may be a need for synchronizing data 
sampling to specific time stamps or to other data channels.

> I am trying to developing a DAQ IP
> My DAQ IP is not processing any data, simply acquires samples from ADC.
What ADC? With what device? What platform, what HDL and what toolchain?

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