Hello everyone I recently started coding in VHDL(code here is of T flip
flop) and I'm having an error which says "Process clocking is too
complex", and this is with the first code attached below and
surprisingly I the solution too. But I don't know how it worked, code
without error is Second code. I googled about the error for half hour
but couldn't find the satisfying reason. Please help.
First code:
1  LIBRARY ieee;

2  USE ieee.std_logic_1164.all;

3  
4  ENTITY t_ff IS

5  PORT(t,clk,rst:IN STD_LOGIC;

6  q,q_bar:OUT STD_LOGIC);

7  END t_ff;

8  
9  ARCHITECTURE t_ff OF t_ff IS

10  SIGNAL temp: STD_LOGIC;

11  BEGIN

12  PROCESS(clk,rst)

13  BEGIN

14  IF(clk='1' AND clk'event)THEN

15  IF(t='1')THEN temp<= NOT temp;

16  END IF;

17  ELSIF(rst='1')THEN temp<='0';

18  END IF;

19  q<= temp;

20  q_bar<= NOT temp;

21  END PROCESS;

22  END t_ff;

Second code:
1  LIBRARY ieee;

2  USE ieee.std_logic_1164.all;

3  
4  ENTITY t_ff IS

5  PORT(t,clk,rst:IN STD_LOGIC;

6  q,q_bar:OUT STD_LOGIC);

7  END t_ff;

8  
9  ARCHITECTURE t_ff OF t_ff IS

10  SIGNAL temp: STD_LOGIC;

11  BEGIN

12  PROCESS(clk,rst)

13  BEGIN

14  IF(rst='1')THEN temp<='0';

15  ELSIF(clk='1' AND clk'event)THEN

16  IF(t='1')THEN temp<= NOT temp;

17  END IF;

18  END IF;

19  q<= temp;

20  q_bar<= NOT temp;

21  END PROCESS;

22  END t_ff;
