Hello everyone I recently started coding in VHDL(code here is of T flip
flop) and I'm having an error which says "Process clocking is too
complex", and this is with the first code attached below and
surprisingly I the solution too. But I don't know how it worked, code
without error is Second code. I googled about the error for half hour
but couldn't find the satisfying reason. Please help.
First code:
1 | LIBRARY ieee;
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2 | USE ieee.std_logic_1164.all;
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3 |
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4 | ENTITY t_ff IS
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5 | PORT(t,clk,rst:IN STD_LOGIC;
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6 | q,q_bar:OUT STD_LOGIC);
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7 | END t_ff;
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8 |
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9 | ARCHITECTURE t_ff OF t_ff IS
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10 | SIGNAL temp: STD_LOGIC;
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11 | BEGIN
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12 | PROCESS(clk,rst)
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13 | BEGIN
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14 | IF(clk='1' AND clk'event)THEN
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15 | IF(t='1')THEN temp<= NOT temp;
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16 | END IF;
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17 | ELSIF(rst='1')THEN temp<='0';
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18 | END IF;
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19 | q<= temp;
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20 | q_bar<= NOT temp;
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21 | END PROCESS;
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22 | END t_ff;
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Second code:
1 | LIBRARY ieee;
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2 | USE ieee.std_logic_1164.all;
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3 |
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4 | ENTITY t_ff IS
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5 | PORT(t,clk,rst:IN STD_LOGIC;
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6 | q,q_bar:OUT STD_LOGIC);
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7 | END t_ff;
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8 |
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9 | ARCHITECTURE t_ff OF t_ff IS
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10 | SIGNAL temp: STD_LOGIC;
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11 | BEGIN
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12 | PROCESS(clk,rst)
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13 | BEGIN
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14 | IF(rst='1')THEN temp<='0';
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15 | ELSIF(clk='1' AND clk'event)THEN
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16 | IF(t='1')THEN temp<= NOT temp;
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17 | END IF;
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18 | END IF;
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19 | q<= temp;
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20 | q_bar<= NOT temp;
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21 | END PROCESS;
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22 | END t_ff;
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