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VHDL error “Process clocking is too complex.”
von Rocking S. (Company: none) (suanhaas)

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Hello everyone I recently started coding in VHDL(code here is of T flip 
flop) and I'm having an error which says "Process clocking is too 
complex", and this is with the first code attached below and 
surprisingly I the solution too. But I don't know how it worked, code 
without error is Second code. I googled about the error for half hour 
but couldn't find the satisfying reason. Please help.

First code:

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LIBRARY ieee;

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USE ieee.std_logic_1164.all;

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ENTITY t_ff IS

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    PORT(t,clk,rst:IN STD_LOGIC;

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         q,q_bar:OUT STD_LOGIC);

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END t_ff;

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ARCHITECTURE t_ff OF t_ff IS

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SIGNAL temp: STD_LOGIC;

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BEGIN

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    PROCESS(clk,rst)

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    BEGIN

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        IF(clk='1' AND clk'event)THEN

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            IF(t='1')THEN temp<= NOT temp;

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            END IF;

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        ELSIF(rst='1')THEN temp<='0';

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        END IF;

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        q<= temp;

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        q_bar<= NOT temp;

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    END PROCESS;

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END t_ff;


Second code:

1
LIBRARY ieee;

2
USE ieee.std_logic_1164.all;

3
4
ENTITY t_ff IS

5
    PORT(t,clk,rst:IN STD_LOGIC;

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         q,q_bar:OUT STD_LOGIC);

7
END t_ff;

8
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ARCHITECTURE t_ff OF t_ff IS

10
SIGNAL temp: STD_LOGIC;

11
BEGIN

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    PROCESS(clk,rst)

13
    BEGIN

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        IF(rst='1')THEN temp<='0';

15
        ELSIF(clk='1' AND clk'event)THEN

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            IF(t='1')THEN temp<= NOT temp;

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            END IF;

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        END IF;

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        q<= temp;

20
        q_bar<= NOT temp;

21
    END PROCESS;

22
END t_ff;


  


  




  

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    Re: VHDL error “Process clocking is too complex.”
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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Rocking S. wrote:
> I'm having an error which says "Process clocking is too complex"
What part of the toolchain reports that error?

Rocking S. wrote:
> code without error is Second code
So the problem is in the order of clock and reset in the first one. And 
with a closer look it's easy to see: you want a flipflop where the clock 
is dominant against the reset. There is no such component inside a FPGA. 
To get synthesizable code you must write it in a way the synthesizer is 
able to transform to hardware.

BTW: do you know a flipflop with such a behavior at all?

  


  



  

  
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    Re: VHDL error “Process clocking is too complex.”
  


  

    

      von
      
        Rocking sharma (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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> BTW: do you know a flipflop with such a behavior at all?

No, but as I wrote earlier I just started learning VHDL so I was trying 
out few things. Yes I know I'm trying stupid things. But hey can you 
tell me how should I start learning this language?

  


  




  

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    Re: VHDL error “Process clocking is too complex.”
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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The best way is to look how others did it. And to look for the 
synthesizers manual. Because out of the 100% VHDL running well on a 
simulator only about 5% will be synthesizable.
So, VHDL for FPGA is much different than VHDL for simulation. The first 
one is about 5% of the second one.

  


  




  

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