Forum: FPGA, VHDL & Verilog Multi functional push key.

von Fue X. (xiong347)

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Hello all,

I'm new to this forum so any help is appreciated. I am using a soc-de1 
dev board and on this dev board there are 4 push keys but I want to use 
only one push key that can activate different functions depending on how 
many times I activate that push button. For example say I want to 
control a fan with 3 different settings by only using one push key. The 
first setting is activated if the push key is activated once, second 
setting if activated twice, and third setting if activated three times. 
What would be a good approach to creating this?

Thank you.

von (º°)·´¯`·.¸¸.·´¯`·.¸¸.·´¯`·.¸¸.·´¯`·.¸¸.·´¯`·.¸¸.· (Guest)

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Debounce this button, and count the rising edges in a time window.

von Fue X. (xiong347)

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Thank you.

von Lothar M. (lkmiller) (Moderator)

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Fue X. wrote:
> What would be a good approach to creating this?
The definition is ambiguous:
Lets say "speed" instead of "setting" and you have threee speeds "off", 
"slow" and "fast".

Now we have the first approach:
When the fan stands still, and then when the key is pressed once the fan 
should switch to speed "low". Now it will switch to speed "fast" when 
its pressed one again one minute later. And to "off" when its pressed 
again one minute later. To conclude: it will cycle through the three 
speeds like this (p=press and release key, -=one minute, o=off, s=slow, 
key    ---p---p--p--pp----p---ppp---p--pp---
speed  ooossssfffooosfffffoooosfoooosssfoooo

Or the second approach:
When you press the key only once should it switch "off". But when you 
press the key twice in lets say less than one second then it should 
switch to "slow". And if its pressed three times in one second then it 
switches to "fast". So the action will be like this:
key    ---p---pp----p---ppp---p--pp---p---
speed  oooooooosssssooooooffffoooossssoooo

I would expect my fan to behave like approach one. How should yours?

However: the first step is (as already said) always the same sync the 
button to the FPGA clock and afterwards debounce the signal and perform 
an edge detection to it.
What comes next depends on the desired behaviour:
1. When you simply have to cycle through the three speeds, than add a 
counter from 0 to 2. Wrap it around when it reaches 2.
2. When you must implement a behaviour like approach 2, then count the 
key presses and start a timeout counter of eg. 500ms with each keypress. 
When the timeout counter reaches its final value, then that means that 
the last counter value is valid and should be used as the new speed.

BTW: which HDL do you use?

von Fue X. (xiong347)

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Sorry for the ambiguity I should have been more clear. Mine would 
function like the second option which you pretty much nailed. I had a 
similar approach but was having problems visualizing my implementation. 
Thank you so much this was very helpful and I use vhdl along with 
quartus and modelsim.


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