EmbDev.net

Forum: FPGA, VHDL & Verilog for loop and addition


Author: Yoni C. (Company: Gidel) (yonico12344)
Posted on:

Rate this post
0 useful
not useful
1) Hi, I'm trying to write a code that looks like this
localparam NUM_OF_LINES = 2;
localparam ROWS = 2;

genvar i, j;

generate
  for (i = 0; i < NUM_OF_LINES; i = i+1)
    begin: lines_loop 
      for (i = 0; i < NUM_OF_ROWS; i = i+1)
         begin: rows_loop
            always @(posedge clk)
               data[i][j] <= prev_data [i][j];
        end
    end

ofcourse all the regs are declared.
I can't compile it when it's like that, what is the right syntax for 
loop within a loop?


2)

localparam WIDTH = 10;

How can I right an addition command with the width of the parameter?

explanation: I'm trying to do:

data <= data + 1;

when data is the width of WIDTH but I don't want it to do the addition 
with 32 bits so i tried to write "data <= data + WIDTH'h1" but it's not 
working

: Edited by Moderator
Author: Lothar M. (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
Yoni C. wrote:
> I can't compile it when it's like that
What error message do you get?

> what is the right syntax for loop within a loop?
Lets go one step back: do you know, that a 'loop' in a HDL is completely 
different from a loop in C?

To keep things short: a clock inside a HDL loop is a very tricky thing. 
What hardware do you expect for that? What hardware do you want to 
"describe"? (as HDL is read "hardware DESCRIPTION language" you should 
know what hardware you want to describe...)

: Edited by Moderator
Author: Yoni C. (Company: Gidel) (yonico12344)
Posted on:

Rate this post
0 useful
not useful
The messege i get:

Error (10049): Verilog HDL error at arrays.sv(20): value must not be 
assigned to nonvariable "j".

I don't realy understand the deferance between loop in c and verilog.

Author: Duke Scarring (Guest)
Posted on:

Rate this post
0 useful
not useful
Yoni C. wrote:
> for (i = 0; i < NUM_OF_LINES; i = i+1)
> ...
>       for (i = 0; i < NUM_OF_ROWS; i = i+1)
Where is j used?

Author: Yoni C. (Company: Gidel) (yonico12344)
Posted on:

Rate this post
0 useful
not useful
sorry, ofcourse the second for loop is with j

Author: Dussel (Guest)
Posted on:

Rate this post
0 useful
not useful
Yoni C. wrote:
> Error (10049): Verilog HDL error at arrays.sv(20): value must not be
> assigned to nonvariable "j".
Which line is line 20?

Author: Yoni C. (Company: Gidel) (yonico12344)
Posted on:

Rate this post
0 useful
not useful
Dussel wrote:
> Which line is line 20?

for (j = 0; j < NUM_OF_ROWS; j = j+1)

Author: Yoni C. (Company: Gidel) (yonico12344)
Posted on:

Rate this post
0 useful
not useful
Lothar M. wrote:
> To keep things short: a clock inside a HDL loop is a very tricky thing.
> What hardware do you expect for that? What hardware do you want to
> "describe"? (as HDL is read "hardware DESCRIPTION language" you should
> know what hardware you want to describe...)

I want to describe assigning from the registers of "prev_data"
to the registers of "data", both of them are 2 dimention registers 
array.

: Edited by User

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.