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Forum: FPGA, VHDL & Verilog for loop and addition


for loop and addition
von Yoni C. (Company: Gidel) (yonico12344)

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1) Hi, I'm trying to write a code that looks like this
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localparam NUM_OF_LINES = 2;

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localparam ROWS = 2;

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genvar i, j;

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generate

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  for (i = 0; i < NUM_OF_LINES; i = i+1)

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    begin: lines_loop 

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      for (i = 0; i < NUM_OF_ROWS; i = i+1)

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         begin: rows_loop

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            always @(posedge clk)

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               data[i][j] <= prev_data [i][j];

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        end

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    end


ofcourse all the regs are declared.
I can't compile it when it's like that, what is the right syntax for 
loop within a loop?


2)

localparam WIDTH = 10;

How can I right an addition command with the width of the parameter?

explanation: I'm trying to do:

data <= data + 1;

when data is the width of WIDTH but I don't want it to do the addition 
with 32 bits so i tried to write "data <= data + WIDTH'h1" but it's not 
working

  


  



  

  
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    Re: for loop and addition
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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Yoni C. wrote:
> I can't compile it when it's like that
What error message do you get?

> what is the right syntax for loop within a loop?
Lets go one step back: do you know, that a 'loop' in a HDL is completely 
different from a loop in C?

To keep things short: a clock inside a HDL loop is a very tricky thing. 
What hardware do you expect for that? What hardware do you want to 
"describe"? (as HDL is read "hardware DESCRIPTION language" you should 
know what hardware you want to describe...)

  


  



  

  
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    Re: for loop and addition
  


  

    

      von
      
        Yoni C.
            (Company: Gidel)
        (yonico12344)
        
      
      


      
    


    

      
    

    

    

  
  


  

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The messege i get:

Error (10049): Verilog HDL error at arrays.sv(20): value must not be 
assigned to nonvariable "j".

I don't realy understand the deferance between loop in c and verilog.

  


  




  

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    Re: for loop and addition
  


  

    

      von
      
        Duke Scarring (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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Yoni C. wrote:
> for (i = 0; i < NUM_OF_LINES; i = i+1)
> ...
>       for (i = 0; i < NUM_OF_ROWS; i = i+1)
Where is j used?

  


  




  

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    Re: for loop and addition
  


  

    

      von
      
        Yoni C.
            (Company: Gidel)
        (yonico12344)
        
      
      


      
    


    

      
    

    

    

  
  


  

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sorry, ofcourse the second for loop is with j

  


  




  

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    Re: for loop and addition
  


  

    

      von
      
        Dussel (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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Yoni C. wrote:
> Error (10049): Verilog HDL error at arrays.sv(20): value must not be
> assigned to nonvariable "j".
Which line is line 20?

  


  




  

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    Re: for loop and addition
  


  

    

      von
      
        Yoni C.
            (Company: Gidel)
        (yonico12344)
        
      
      


      
    


    

      
    

    

    

  
  


  

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Dussel wrote:
> Which line is line 20?

for (j = 0; j < NUM_OF_ROWS; j = j+1)

  


  




  

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    Re: for loop and addition
  


  

    

      von
      
        Yoni C.
            (Company: Gidel)
        (yonico12344)
        
      
      


      
    


    

      
    

    

    

  
  


  

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Lothar M. wrote:
> To keep things short: a clock inside a HDL loop is a very tricky thing.
> What hardware do you expect for that? What hardware do you want to
> "describe"? (as HDL is read "hardware DESCRIPTION language" you should
> know what hardware you want to describe...)

I want to describe assigning from the registers of "prev_data"
to the registers of "data", both of them are 2 dimention registers 
array.

  


  



  

  
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