no interface for function call, slice or indexed name in association

library IEEE;

use IEEE.std_logic_1164.all;

entity main is port (

  select_reg : in std_logic_vector(3 downto 0);

  read, write, reset : in std_logic;

  idata : in std_logic_vector(7 downto 0);

  odata : out std_logic_vector(7 downto 0)

  );

end entity;

architecture rtl  of main is

  component reg is port (

  d : in std_logic_vector(7 downto 0);

  clk : in std_logic;

  q : out std_logic_vector(7 downto 0));

  end component;

  signal d, q : std_logic_vector(7 downto 0) := "00000000";

  signal clk : std_logic := '1';

  type regs is array (0 to 15) of std_logic_vector(7 downto 0);

  signal in_regs : regs;

  signal out_regs : regs;

begin

  reg1: reg port map (in_regs(0)=>d, clk=>clk, out_regs(0)=>q);

  reg2: reg port map (in_regs(1)=>d, clk=>clk, out_regs(1)=>q);

  reg3: reg port map (in_regs(2)=>d, clk=>clk, out_regs(2)=>q);

  reg4: reg port map (in_regs(3)=>d, clk=>clk, out_regs(3)=>q);

  reg5: reg port map (in_regs(4)=>d, clk=>clk, out_regs(4)=>q);

  reg6: reg port map (in_regs(5)=>d, clk=>clk, out_regs(5)=>q);

  reg7: reg port map (in_regs(6)=>d, clk=>clk, out_regs(6)=>q);

  reg8: reg port map (in_regs(7)=>d, clk=>clk, out_regs(7)=>q);

  reg9: reg port map (in_regs(8)=>d, clk=>clk, out_regs(8)=>q);

  reg10: reg port map (in_regs(9)=>d, clk=>clk, out_regs(9)=>q);

  reg11: reg port map (in_regs(10)=>d, clk=>clk, out_regs(10)=>q);

  reg12: reg port map (in_regs(11)=>d, clk=>clk, out_regs(11)=>q);

  reg13: reg port map (in_regs(12)=>d, clk=>clk, out_regs(12)=>q);

  reg14: reg port map (in_regs(13)=>d, clk=>clk, out_regs(13)=>q);

  reg15: reg port map (in_regs(14)=>d, clk=>clk, out_regs(14)=>q);

  reg16: reg port map (in_regs(15)=>d, clk=>clk, out_regs(15)=>q);

  process

    variable select_number : integer;

  begin

    select_number := 0;

    if select_reg(3) = '1' then

      select_number := 1;

    end if;

    if select_reg(2) = '1' then

      select_number := select_number + 2;

    end if;

    if select_reg(1) = '1' then 

      select_number := select_number + 4;

    end if;

    if select_reg(0) = '1' then

      select_number := select_number + 8;

    end if;

    if read = '1' then

      odata <= out_regs(select_number);

    elsif write = '1' then

         odata <= "00000000";  

      in_regs(select_number) <= idata;

    else

      odata <= "00000000";

    end if;

  end process;

end architecture;

main.vhd:29:40: no interface for function call, slice or indexed name in association

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main.vhd:44:42: no interface for function call, slice or indexed name in association

ghdl: compilation error