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Forum: FPGA, VHDL & Verilog no interface for function call, slice or indexed name in association


von amir (Guest)


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hi guys

what does this error means?
1
no interface for function call, slice or indexed name in association

my code is this
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity main is port (
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  select_reg : in std_logic_vector(3 downto 0);
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  read, write, reset : in std_logic;
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  idata : in std_logic_vector(7 downto 0);
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  odata : out std_logic_vector(7 downto 0)
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  );
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end entity;
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architecture rtl  of main is
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  component reg is port (
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  d : in std_logic_vector(7 downto 0);
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  clk : in std_logic;
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  q : out std_logic_vector(7 downto 0));
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  end component;
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  signal d, q : std_logic_vector(7 downto 0) := "00000000";
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  signal clk : std_logic := '1';
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  type regs is array (0 to 15) of std_logic_vector(7 downto 0);
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  signal in_regs : regs;
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  signal out_regs : regs;
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begin
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  reg1: reg port map (in_regs(0)=>d, clk=>clk, out_regs(0)=>q);
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  reg2: reg port map (in_regs(1)=>d, clk=>clk, out_regs(1)=>q);
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  reg3: reg port map (in_regs(2)=>d, clk=>clk, out_regs(2)=>q);
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  reg4: reg port map (in_regs(3)=>d, clk=>clk, out_regs(3)=>q);
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  reg5: reg port map (in_regs(4)=>d, clk=>clk, out_regs(4)=>q);
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  reg6: reg port map (in_regs(5)=>d, clk=>clk, out_regs(5)=>q);
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  reg7: reg port map (in_regs(6)=>d, clk=>clk, out_regs(6)=>q);
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  reg8: reg port map (in_regs(7)=>d, clk=>clk, out_regs(7)=>q);
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  reg9: reg port map (in_regs(8)=>d, clk=>clk, out_regs(8)=>q);
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  reg10: reg port map (in_regs(9)=>d, clk=>clk, out_regs(9)=>q);
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  reg11: reg port map (in_regs(10)=>d, clk=>clk, out_regs(10)=>q);
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  reg12: reg port map (in_regs(11)=>d, clk=>clk, out_regs(11)=>q);
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  reg13: reg port map (in_regs(12)=>d, clk=>clk, out_regs(12)=>q);
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  reg14: reg port map (in_regs(13)=>d, clk=>clk, out_regs(13)=>q);
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  reg15: reg port map (in_regs(14)=>d, clk=>clk, out_regs(14)=>q);
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  reg16: reg port map (in_regs(15)=>d, clk=>clk, out_regs(15)=>q);
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  process
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    variable select_number : integer;
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  begin
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    select_number := 0;
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    if select_reg(3) = '1' then
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      select_number := 1;
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    end if;
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    if select_reg(2) = '1' then
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      select_number := select_number + 2;
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    end if;
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    if select_reg(1) = '1' then 
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      select_number := select_number + 4;
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    end if;
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    if select_reg(0) = '1' then
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      select_number := select_number + 8;
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    end if;
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    if read = '1' then
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      odata <= out_regs(select_number);
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    elsif write = '1' then
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         odata <= "00000000";  
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      in_regs(select_number) <= idata;
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    else
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      odata <= "00000000";
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    end if;
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  end process;
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end architecture;


and here is the log that ghdl has throwed!!!
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main.vhd:29:40: no interface for function call, slice or indexed name in association
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main.vhd:30:40: no interface for function call, slice or indexed name in association
3
main.vhd:31:40: no interface for function call, slice or indexed name in association
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main.vhd:32:40: no interface for function call, slice or indexed name in association
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main.vhd:33:40: no interface for function call, slice or indexed name in association
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main.vhd:34:40: no interface for function call, slice or indexed name in association
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main.vhd:35:40: no interface for function call, slice or indexed name in association
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main.vhd:36:40: no interface for function call, slice or indexed name in association
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main.vhd:37:40: no interface for function call, slice or indexed name in association
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main.vhd:38:41: no interface for function call, slice or indexed name in association
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main.vhd:39:42: no interface for function call, slice or indexed name in association
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main.vhd:40:42: no interface for function call, slice or indexed name in association
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main.vhd:41:42: no interface for function call, slice or indexed name in association
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main.vhd:42:42: no interface for function call, slice or indexed name in association
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main.vhd:43:42: no interface for function call, slice or indexed name in association
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main.vhd:44:42: no interface for function call, slice or indexed name in association
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ghdl: compilation error


thank you

von Duke Scarring (Guest)


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amir wrote:
> reg1: reg port map (in_regs(0)=>d, clk=>clk, out_regs(0)=>q);
try with
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  reg1: reg 
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  port map (
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    d   => in_regs(0),
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    clk => clk,
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    q   => out_regs(0)
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  );

or much shorter:
1
out_regs <= in_regs when rising_edge(clk);

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