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Forum: FPGA, VHDL & Verilog array of an entity


Author: amir (Guest)
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hi guys

I have register entity in my program.
the question is there will be 16 different registers in a very simple 
cpu. I should access each of these registers and according to read , 
write and select_register inputs, read or write on the selected 
register.

my problem is how to define an array of registers that let me read or 
write on them.

I mean something like this:

----type reg16 is array (0 to 15) of reg;----

thank you

Author: P. K. (pek)
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Try something like this:
entity GENREG is
  generic (
    WIDTH : integer := 8);           -- register width
  port (
    SysxC      : in  std_logic;
    -- Register input path
    ReqInxSO   : out std_logic;
    AckInxSI   : in  std_logic;
    InxDI      : in  unsigned(WIDTH-1 downto 0);
    -- Register output path
    ReqOutxSI  : in  std_logic;
    AckOutxSO  : out std_logic;
    OutxDO     : out unsigned(WIDTH-1 downto 0);
    -- Status
    RegBusyxSO : out std_logic;
    -- CSR interface
    SoftResxSI : in  std_logic := '0'
        );                                                   
end GENREG;

This is generic width inside the register. If you want a number of 
entities instantiated, try something like:
REG : for i in 0 to NR_REG-1 generate
  -- Instances
end generate REG;  

: Edited by User
Author: Lothar Miller (lkmiller) (Moderator)
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amir wrote:
> my problem is how to define an array of registers that let me read or
> write on them.
First define one of those 'reg' s. Maybe it's good to use a record for 
it.
Then  transfer this definition in a package and define the register set 
exactly the way you already did.

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