Hello! I have to write a testbench for I2C. I have an inout SDA port, which I drive to either zero or high impedance state in the module.I want to make sure that on the 9th clock cycle, when the SDA port is driven to a high impedance state for the slave to issue an acknowledge, the test bench drives the port low, indicating successful acknowledgement by the slave. Currently, I know when I want to drive the port low, this cycle is marked by an IO signal in simulation which goes high on the 9th clock cycle. The function should be something like this : //reg IO; //IO is controlled in the testbench, not exported from module. if (IO) SDA = 1'b0; else SDA = SDA; /// The following approach did not work. assign SDA = IO? 1'b0 : SDA;
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The problem may be that you never set SDA = 1'bZ when IO===0. So your SDA signal is always driven by the test bench. ( I am not sure if 1'bZ is the correct notation for high impedance in Verilog, you have to look up)
Ahmed A. wrote: > which I drive to either zero or high impedance You don't. Instead you built a latch... http://electronics.stackexchange.com/questions/219776/what-exactly-does-a-high-impedance-imply-in-verilog
assign SDA = IO? 1'b0 : 1'bz; This works. Thank you!
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