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Forum: FPGA, VHDL & Verilog Verilog synthesis - Too many always blocks, or too long datapath or?


Author: Zwergi (Guest)
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Hi!

I hope someone can help me!

I'm trying to write a receiver that recognizes different pattern of bits 
sequentially. I'm using a MachXO3 FPGA and Lattice Diamond software.
The inputted signal is 13.56MHz and I'm want to sample each period 8 
times. I have a separate counter process that counts 8 samples for 8 
periods and then starts over.
The computation is then done on the same input clock (108.48MHz) and 
according to the counter values.

The code is actually a simple detection of flags using if-else, but I 
cannot make it work.

I have scheduled different kinds of detections within different always 
blocks, because it didn't work with everything within one block. I hoped 
it's a problem of the pathlength (I clock it with 108.48MHz) and tried 
to make the execution parallel, but this didn't work neither.

The same code without the lines 218-307 works fine, but as soon as I 
insert the these lines everything goes wrong and even the part that went 
fine before is not working correctly anymore.

Can someone give me a hint why this is not working? Is it because there 
are incomplete specified if-else cases or is it simply that my 
pathlengths are getting too long? Shouldn't I use so many always blocks 
or should I use blocking assignments instead of nonblocking ones?

Please help me!

Author: Lothar M. (lkmiller) (Moderator)
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Zwergi wrote:
> I hoped it's a problem of the pathlength (I clock it with 108.48MHz)
Theres no place for "hope" and "whish". Simply set a clock constraint. 
Then the almighty "toolchain" will tell you whether its working or nor.

> The same code without the lines 218-307 works fine, but as soon as I
> insert the these lines everything goes wrong and even the part that went
> fine before is not working correctly anymore.
> Can someone give me a hint why this is not working?
Maybe your "lock", the "receiveenable", but for sure the "sigin" are 
asynchronous external signals. The MUST be synched to the clock before 
being used by flipflops clocked with that clock. Otherwise you will 
encounter spurious curious problems now and then.

> but this didn't work neither.
How did you figure that out?
Did you run a simple simulation at least? See it that way: the simulator 
is the FPGA debugger. Of course you must observe some simple rules to 
get the same results in simulation and reality: and the most simple is 
that every external signal must be synchronized to the clock.

Author: Zwergi (Guest)
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Hi!

Thanks a lot for your advices! The first one already worked out. I 
simply clocked it too fast and the constraints told me that. That's why 
it worked in the simulation and not in synthesis.

I took down the frequency and also syncronize every external signal now 
and it's working fine.

> Theres no place for "hope" and "whish".
I've prayed for help and got it here so hoping and wishing worked out^^

Thank you soooo much!

Author: Lothar M. (lkmiller) (Moderator)
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Zwergi wrote:
> I've prayed for help and got it here so hoping and wishing worked out^^
That might not work always... :-D

> Thank you soooo much!
You're welcome ;-)

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