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#4920642
Hi! I hope someone can help me! I'm trying to write a receiver that recognizes different pattern of bits sequentially. I'm using a MachXO3 FPGA and Lattice Diamond software. The inputted signal is 13.56MHz and I'm want to sample each period 8 times. I have a separate counter process that counts 8 samples for 8 periods and then starts over. The computation is then done on the same input clock (108.48MHz) and according to the counter values. The code is actually a simple detection of flags using if-else, but I cannot make it work. I have scheduled different kinds of detections within different always blocks, because it didn't work with everything within one block. I hoped it's a problem of the pathlength (I clock it with 108.48MHz) and tried to make the execution parallel, but this didn't work neither. The same code without the lines 218-307 works fine, but as soon as I insert the these lines everything goes wrong and even the part that went fine before is not working correctly anymore. Can someone give me a hint why this is not working? Is it because there are incomplete specified if-else cases or is it simply that my pathlengths are getting too long? Shouldn't I use so many always blocks or should I use blocking assignments instead of nonblocking ones? Please help me!