# Forum: FPGA, VHDL & Verilog Resizing an image on FPGA

 Author: Harvey (Guest) Posted on: 2017-03-01 08:39

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Recently I was doing a project on FPGA in Verilog or VHDL

The project goes like this:

A 100*100 resolution image（24 bits true color） need to be downsized to
75*75(also 24 bits true color).

The hint tutor provided is :

1. first segment the image into 4*4 blocks and then mapping them to a
3*3 blocks.

2. Writing a LUT to achieve mapping method.

I've got no idea how to mapping the pixels.
Can anyone help me?

 Author: P. K. (pek) Posted on: 2017-03-01 09:32

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Harvey wrote:
> mapping method

If the mapping method is not give, I'd use linear interpolation (in 2
dimensions) to do this.

The mentioned LUT possible refers to the weights required in your
interpolation.

Once you solved the task for reducing a 4x4 part of the image to the
required 3x3, you can feed all other 4x4-parts of the picture to your
small converter.

 Author: Lothar Miller (lkmiller) (Moderator) Posted on: 2017-03-01 09:51

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Harvey wrote:
> The hint tutor provided is :
> 1...
> 2...
> I've got no idea how to mapping the pixels.
For those 2 tasks at first step you do not need any FPGA, just a sheet
of paper and "brain 1.0".

> 1. first segment the image into 4*4 blocks and then mapping them to a
> 3*3 blocks.
Arrange the image in 4x4 blocks means you have to spilt up the 100x100
pixels in 25x25 of 4x4 pixel blocks.
And then you nust find a method to recalculate a 3x3 block out of a 4x4
block. Lets assume we have a simple b&w picture and lets say B are the
Pixels of the BIG array, ans S are the pixels of the SMALL array:
  B00 B01 B02 B03 S00 S01 S02 B10 B11 B12 B13 S10 S11 S12 B20 B21 B22 B23 S20 S21 S22 B30 B31 B32 B33 
So, S00 consists of a mean value from the pixels B00, B01, B10 and B11:
S00 = (B00+B01+B10+B11)/4
If you have three colors (24 bit = 3*8 bit) you must find an adequate
method to sum up each of the colors.

> 2. Writing a LUT to achieve mapping method.
A simple straightforward LUT for a pixel ist fairly big, as it has to be
addressed by 96 bits (4*24bits: e.g. B00&B01&B10&B11) and the output is
24 bits (e.g. S00). So you will hav to find a way to reduce the input
vector before sccessing the LUT.

All in all it is NOT a job for a beginner. And it is NOT done this day.

Harvey wrote:
> Recently I was doing a project on FPGA in Verilog or VHDL
What have you done with an FPGA before this? How did you start FPGA
design? Did you already do the flashing LED, the "Hello world!" of
hardware? Did you implement some interfaces (RS232, SPI,...) to get
known to your HDL?

 Author: Svenska (Guest) Posted on: 2017-03-01 15:21

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Draw the original picture on paper, then divide in small blocks of 4x4
pixels each. You get 25 by 25 blocks. The new picture has exactly the
same number of blocks with the same coordinates, except that the new
blocks are only 3x3 pixels each, so that the new picture is smaller.

Which means that you need a mapping which takes 16 pixels (384 bits) as
input and produces 9 pixels (216 bits) as output. You can't do this with
a LUT (it would require 2^384*216/8 bytes of memory), but you can
describe an algorithm to do this.

A simple approach could be to keep the corner pixels, take an average of
two pixels for the remaining boundary pixel, and take an average of four
pixels for the center pixel. Linear interpolation of the colors may
produce better results and doing the interpolation in a different
colorspace may be even better. What looks best depends on the image type
(what works for drawings usually does not work well for photos and vice
versa).

Note that a local algorithm (working on each block separately) does not
necessary interpolate well on a global scale, i.e. for some inputs, your
output image will look blocky or produce visual artifacts.

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