DSP_Arch_Student wrote:
> where the carry in signal is not be registered at all.
An adder is a completly registerless, combinatorial design. So is yours:
no clock, no registers.
And now: what do you mean with "not registered"?
One major flaw in your design ist, that you don't know about how signals
behave in a process. They keep(!!) their value throughout(!!) the whole
process. And at the end of the process they get the last assigned value.
Think about that.
Lets start here with c_internal='0' and c='1'. On the right side of all
the assginments througout the process c_internal is '0':
P1 : PROCESS (a, b, c, c_internal)
BEGIN
c_internal <= c;  c_internal gets a new value that will possibly be transferred at the end of the process
for i in 0 to 31 loop
result(i) <= a(i) xor b(i) xor c_internal;  c_internal IS '0' HERE
c_internal <= (a(i) and b(i)) or (a(i) and c_internal) or (b(i) and c_internal);  c_internal IS '0' HERE, it may get a new value at the end of the process
end loop;
cout <= c_internal;  c_internal IS '0' here, so cout is '0' also
END PROCESS P1;  And finally c_internal here gets the last assigned value from three lines above

In this case here c_internal must be a variable. Variables virtually
take over the assigned value "immediately". Lets start again with
c_internal='0' and c='1':
ARCHITECTURE adder_32bit OF hmk2_32bitAdder IS
BEGIN
P1 : PROCESS (a, b, c, c_internal)
variable c_internal : std_logic;
BEGIN
c_internal := c;  always initialise the variable!
for i in 0 to 31 loop  surprise, surprise: now HERE c_internal IS '1'
result(i) <= a(i) xor b(i) xor c_internal;
c_internal := (a(i) and b(i)) or (a(i) and c_internal) or (b(i) and c_internal);
end loop;
cout <= c_internal;
END PROCESS P1;
END ARCHITECTURE adder_32bit;

But be aware that variables in processes are not like variables in C
programs (as VHDL is not a programming language, but a description
language. just keep it in mind, you will find out further on)...