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Forum: FPGA, VHDL & Verilog modelsim simulaiton


von KAYHAN Ç. (Company: gazi) (kayooo)


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hello
ı  made a fifo register with 9 bit wide and 8 bit deep

when ı make a simulation  wi or ri signal gives an error.
simulaiton says that  wi<= wi+1 or ri <=ri +1 dont be  make.
 but  my codes from the book . so there is no error in vhdl file.
but simulaiton dont work .
can any one help me please.

von P. K. (pek)


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KAYHAN Ç. wrote:
> when ı make a simulation  wi or ri signal gives an error.

What does the error message say?

von ulf (Guest)


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Hello

There is not line, where wrinc goes high. So the "elsif (wrinc='1') 
never get's true.

von KAYHAN Ç. (Company: gazi) (kayooo)


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# ** Fatal: (vsim-3421) Value 8 for ri is out of range 0 to 7.
 Time: 23 ps  Iteration: 1  Process: /fifo_tb/dut/line__61 File: 
C:/Users/kayhan/modelsim/fifo.vhd
# Fatal error in Process line__61 at C:/Users/kayhan/modelsim/fifo.vhd 
line 69
#
# HDL call sequence:
# Stopped at C:/Users/kayhan/modelsim/fifo.vhd 69 Process line__61
#

this is the error messege.

von Svenska (Guest)


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A range value of 0 to 7 corresponds to three bits.
A range value of 0 to 255 corresponds to eight bits.

von P. K. (pek)


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KAYHAN Ç. wrote:
> # ** Fatal: (vsim-3421) Value 8 for ri is out of range 0 to 7.
>  Time: 23 ps  Iteration: 1  Process: /fifo_tb/dut/line__61 File:

I assume that your Modelsim does not do an automatic wrap-around of your 
limited integer.
I'd take an unsigned(2 downto 0) instead, this will be fine.

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