Im back here asking yet another question. I'm done doing up my VHDL
codes, and when i tried to upload the codes into my DE2 Altera
Board(Cyclone II EP2C35F672C6N), it seems that it doesnt work even
though it shows "SUCCESSFUL" upon uploading using Quartus II 12.1
(64Bit). Tried using via JTAG and also Active Serial but still to no
avail. Im not too sure if it is the coding that is wrong or simply the
process of me programming the board.
If any of you can point out the mistakes I did, it would be greatly
appreciated and I'll be thankful. Im still a beginner at VHDL so it is a
little bit messy.
here are the codes, and also the attached file of what im currently
facing. The codes shown here are my Main LCD, The Controller and also
Clock Div is in the attached.
Usually the upload process works if there is the green "successful"
I don't read the code because I think you should simulate and test it
with modelsim, so the answer if it works can only be given by yourself!
Its often a good idea to start with a very generic example (just a
counter and a blinking led) to test the toolchain and see if you
- flash the right binary
- the upload process works
Did you set the correct pins in your design?
Youtube-Video "Programming Intel (Altera) FPGAs on the DE0, DE1 or DE2 (Sec 4-4D )"
Did you simulate your design?
My approach is: first simulate, 2nd synthesize
I stronly suggest: avoid ieee.std_logic_unsigned.all, use
Why did you have two reset signals (iRST_N and reset)?
I attached a small testbench. The simulation stops with out-of-range
# ** Fatal: (vsim-3421) Value 2 is out of range 0 to 1.
# Time: 30 ns Iteration: 0 Process: /lcd_main_testbench/dut/always File: LCD_Main.vhd
# Fatal error in Process always at LCD_Main.vhd line 114
thank you for taking the time to test it out for me, it is greatly
appreciated! I'll go and review again my codes and will test it out with
your testbench! Thank you again Duke!
SW is missing and sclk is not needed therein.
Afkar O. wrote:> it seems that it doesnt work
Your startcount prohibits any proper function of this this design. This
counter is not limited just by the definition "rango 0 to 1". You must
handle the overflow yourself.
Here this code results in the curious behaviour that startcount is
synthesized to 1 bit that toggles every clock cycle due to "startcount
As Duke said already: you MUST run a simulation. The simulator is the
debugger of a FPGA design.