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HELP! Programming of DE2 Altera Board.
von Afkar O. (Company: nanyang polytechnic) (afkarsosman)

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Hi,

Im back here asking yet another question. I'm done doing up my VHDL 
codes, and when i tried to upload the codes into my DE2 Altera 
Board(Cyclone II EP2C35F672C6N), it seems that it doesnt work even 
though it shows "SUCCESSFUL" upon uploading using Quartus II 12.1 
(64Bit). Tried using via JTAG and also Active Serial but still to no 
avail. Im not too sure if it is the coding that is wrong or simply the 
process of me programming the board.

If any of you can point out the mistakes I did, it would be greatly 
appreciated and I'll be thankful. Im still a beginner at VHDL so it is a 
little bit messy.

here are the codes, and also the attached file of what im currently 
facing. The codes shown here are my Main LCD, The Controller and also 
Clock Div is in the attached.

1
LIBRARY IEEE;

2
USE IEEE.STD_LOGIC_1164.ALL;

3
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

4
5
ENTITY LCD_Main IS 

6
  PORT ( clk : IN std_logic;

7
      iRST_N : IN std_logic;

8
          SW : IN std_logic_vector(17 downto 0);

9
       reset : IN std_logic;

10
      switch : IN std_logic;

11
     switch2 : IN std_logic;

12
     

13
    LCD_DATA : OUT std_logic_vector(7 downto 0);

14
      LCD_RW : OUT std_logic;

15
      LCD_ON : OUT std_logic;

16
    LCD_BLON : OUT std_logic;

17
      LCD_RS : OUT std_logic;

18
      LCD_EN : OUT std_logic:='0' 

19
       );

20
END LCD_Main;

21
22
ARCHITECTURE LCDBody of LCD_Main is

23
  

24
  CONSTANT LCD_INITIAL:std_logic_vector(7 downto 0):="00000000";

25
  CONSTANT LCD_LINE1:std_logic_vector(7 downto 0):= "00000100";

26
  CONSTANT LCD_CH_LINE:std_logic_vector(7 downto 0):=LCD_LINE1+16;

27
  CONSTANT LCD_LINE2:std_logic_vector(7 downto 0):=LCD_LINE1+16+1;

28
  CONSTANT LUT_SIZE:std_logic_vector(7 downto 0):=(LCD_LINE2+50)+1;

29
  

30
  SIGNAL LUT_DATA:std_logic_vector (11 downto 0):=x"000";--In hex    

31
--  SIGNAL count2 : integer range 0 to 65535 := 0;

32
  SIGNAL LUT_INDEX:std_logic_vector(7 downto 0):="00000000";

33
  SIGNAL mLCD_DONE:std_logic:='0';

34
 -- SIGNAL mLCD_ST:std_logic_vector(5 downto 0):="000000";

35
  SIGNAL mLCD_ST:std_logic_vector(1 downto 0):="00";

36
  SIGNAL mDLY:std_logic_vector(27 downto 0):=x"0000000";--In hex

37
  SIGNAL mLCD_Start:std_logic:='0';

38
  SIGNAL mLCD_DATA:std_logic_vector(7 downto 0):="00000000";

39
  SIGNAL mLCD_RS:std_logic:='0';

40
  SIGNAL sclk:std_logic:='0';

41
  SIGNAL startcount : integer range 0 to 1:=0;

42
  SIGNAL D1,D2,D3,D4,D5,D6 : std_logic_vector (11 downto 0):=x"130";

43
--  SIGNAL D1,D2,D3,D4,D5,D6 : std_logic_vector (11 downto 0);

44
45
  COMPONENT LCD_controller IS

46
       PORT( iCLK,iRS,iRST_N,istart : IN std_logic;

47
                              iDATA : IN std_logic_vector(7 downto 0);

48
                              oDone : OUT std_logic;

49
                           LCD_DATA : OUT std_logic_vector(7 downto 0);

50
                             LCD_RW : OUT std_logic;

51
                             LCD_RS : OUT std_logic;

52
                             LCD_EN : OUT std_logic

53
           );

54
  END COMPONENT LCD_controller;

55
  

56
  COMPONENT clk_div IS

57
         PORT ( iCLK: IN std_logic;

58
                sclk: OUT std_logic

59
               );

60
  END COMPONENT clk_div; 

61
  

62
  BEGIN      

63
       U0:LCD_controller 

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       PORT MAP(

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                  iCLK => clk,

66
                   iRS => mLCD_RS,

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                iRST_N => iRST_N,

68
                istart => mLCD_START,

69
                 iDATA => mLCD_DATA,

70
                 oDone => mLCD_DONE,

71
              LCD_DATA => LCD_DATA,

72
                LCD_RW => LCD_RW,

73
                LCD_RS => LCD_RS,

74
                LCD_EN => LCD_EN

75
                );

76
                

77
        U1:clk_div 

78
        PORT MAP( iCLK => clk,

79
                  sclk => sclk

80
                 ); 

81
                       

82
    LCD_ON <= '1';

83
    LCD_BLON <= '1';

84
    

85
always : process(clk,reset,sclk)

86
    Begin

87
      IF(SW(0)='1')THEN

88
      D1 <= x"132";

89
      ELSIF(SW(1)='1')THEN

90
      D2 <= x"133";

91
      END IF;

92
      

93
      IF(reset = '1')THEN

94
          LUT_INDEX <= "00000000";

95
          --mLCD_ST <= "000000";

96
          mLCD_ST <= "00";

97
          --mDLY <= x"0000000";

98
          mLCD_DATA <= "00000000";

99
          mLCD_START <= '0';

100
          mLCD_RS <= '0';

101
          

102
          startcount <= 0;

103
          D1 <= x"130";

104
          D2 <= x"130";

105
          D3 <= x"130";

106
          D4 <= x"130";

107
          D5 <= x"130";

108
          D6 <= x"130";

109
      

110
----------LCD Line 1--------------

111
        

112
          

113
      ELSIF(rising_edge(clk))THEN

114
        startcount <= startcount + 1;

115
          IF (startcount = 1)THEN

116
            

117
            IF(LUT_INDEX < LUT_SIZE)THEN

118
              case mLCD_ST is

119
                  when "00" => mLCD_DATA <= LUT_DATA(7 downto 0);

120
                          mLCD_RS   <= LUT_DATA(8);

121
                          mLCD_START<= '1';

122
                          mLCD_ST   <= "01";

123
              

124
                  when "01" => IF(mLCD_DONE = '1') THEN

125
                          mLCD_START <= '0';

126
                          mLCD_ST    <= "10";

127
                         END IF;

128
                          

129
                  when "10" => IF(switch = '1')THEN

130
                          IF(LUT_DATA = x"080")THEN

131
                            mLCD_ST <= "11";

132
                          END IF;

133
                         END IF; 

134
                            

135
                  when "11" => LUT_INDEX <= LUT_INDEX + 1;

136
                         mLCD_ST   <= "00";

137
              end case;

138
            ELSE

139
                IF(sclk = '1')THEN

140
                  LUT_INDEX <= LCD_INITIAL;

141
                END IF;

142
            END IF;

143
            

144
          END IF;

145
      END IF;

146
END PROCESS always;    

147
148
149
150
----READING OF LCD COMMAND----

151
check:process(LUT_INDEX)

152
      begin

153
154
  case LUT_INDEX is  

155
   when LCD_INITIAL+0=>LUT_DATA<=(x"030");

156
   when LCD_INITIAL+1=>LUT_DATA<=(x"00C");         

157
   when LCD_INITIAL+2=>LUT_DATA<=(x"001");          

158
   when LCD_INITIAL+3=>LUT_DATA<=(x"006");           

159
   when LCD_INITIAL+4=>LUT_DATA<=(x"080");

160
   

161
   

162
163
   

164
   when LCD_LINE1 + 1 => LUT_DATA<=(x"130");

165
   when LCD_LINE1 + 2 => LUT_DATA<=(x"130");

166
   when LCD_LINE1 + 3 => LUT_DATA<=(x"130");

167
   when LCD_LINE1 + 4 => LUT_DATA<=(D6);

168
   when LCD_LINE1 + 5 => LUT_DATA<=(D5);

169
   when LCD_LINE1 + 6 => LUT_DATA<=(x"13a");

170
   when LCD_LINE1 + 7 => LUT_DATA<=(D4);

171
   when LCD_LINE1 + 8 => LUT_DATA<=(D3);

172
   when LCD_LINE1 + 9 => LUT_DATA<=(x"13a");

173
   when LCD_LINE1 + 10=> LUT_DATA<=(D2);

174
   when LCD_LINE1 + 11=> LUT_DATA<=(D1);

175
--   when LCD_LINE1 + 12=> LUT_DATA<=(x"130");

176
--   when LCD_LINE1 + 13=> LUT_DATA<=(x"130");

177
--   when LCD_LINE1 + 14=> LUT_DATA<=(x"130");

178
--   when LCD_LINE1 + 15=> LUT_DATA<=(x"130");

179
--   when LCD_LINE1 + 16=> LUT_DATA<=(x"130");  

180
   when others => LUT_DATA <= (x"000");

181
182
   end case;   

183
184
  end process check; 

185
end LCDBody;


  


  




  

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    Re: HELP! Programming of DE2 Altera Board.
  


  

    

      von
      
        ui (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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Usually the upload process works if there is the green "successful" 
message.
I don't read the code because I think you should simulate and test it 
with modelsim, so the answer if it works can only be given by yourself!

Its often a good idea to start with a very generic example (just a 
counter and a blinking led) to test the toolchain and see if you
- flash the right binary
- the upload process works

  


  




  

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    Re: HELP! Programming of DE2 Altera Board.
  


  

    

      von
      
        Duke Scarring (Guest)
      
      


      
    


    

      
    

    

    

      

      

      Attached files:


      

    

  
  


  

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Did you set the correct pins in your design?
https://www.youtube.com/watch?v=UMfxhZcW9YA

Did you simulate your design?
My approach is: first simulate, 2nd synthesize

I stronly suggest: avoid ieee.std_logic_unsigned.all, use 
ieee.numeric_std.all instead.

Why did you have two reset signals (iRST_N and reset)?

I attached a small testbench. The simulation stops with out-of-range 
error:
1
# ** Fatal: (vsim-3421) Value 2 is out of range 0 to 1.

2
#    Time: 30 ns  Iteration: 0  Process: /lcd_main_testbench/dut/always File: LCD_Main.vhd

3
# Fatal error in Process always at LCD_Main.vhd line 114


Duke

  


  




  

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    Re: HELP! Programming of DE2 Altera Board.
  


  

    

      von
      
        Afkar O.
            (Company: nanyang polytechnic)
        (afkarsosman)
        
      
      


      
    


    

      
    

    

    

  
  


  

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Hi Duke!

thank you for taking the time to test it out for me, it is greatly 
appreciated! I'll go and review again my codes and will test it out with 
your testbench! Thank you again Duke!

regards,
Afkar O.

  


  




  

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    Re: HELP! Programming of DE2 Altera Board.
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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This ist is an wrong sensitivity list, leading to a wrong simulation:
1
always : process(clk,reset,sclk)

2
    Begin

3
      IF(SW(0)='1')THEN

4
      D1 <= x"132";

5
      ELSIF(SW(1)='1')THEN

6
      D2 <= x"133";

7
      END IF;

8
9
      IF(reset = '1')THEN

10
          LUT_INDEX <= "00000000";

11
          --mLCD_ST <= "000000";

12
          mLCD_ST <= "00";

13
      :

SW is missing and sclk is not needed therein.

Afkar O. wrote:
> it seems that it doesnt work
Your startcount prohibits any proper function of this this design. This 
counter is not limited just by the definition "rango 0 to 1". You must 
handle the overflow yourself.
Here this code results in the curious behaviour that startcount is 
synthesized to 1 bit that toggles every clock cycle due to "startcount 
<= startcount+1".

As Duke said already: you MUST run a simulation. The simulator is the 
debugger of a FPGA design.

  


  



  

  
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