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Forum: FPGA, VHDL & Verilog HELP! Error messages in Quartus! "Can't infer register"


von Afkar O. (Company: nanyang polytechnic) (afkarsosman)


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Hi!

Im having some error when compiling on my Quartus, what Im trying to 
drive a simple character to my DE2 Altera Board (Cyclone II 
EP2C35F672C6N) LCD.

The Errors are as attached.
Note that this was originally from a previous student, my teacher asked 
me to use his coding to modify it so that i can just display Characters, 
Numbers to the LCD. This previous student's codes was to make a clock 
with the display "00:00:00".

Big advance thanks for any help.

Here are my codes.
1
LIBRARY IEEE;
2
USE IEEE.STD_LOGIC_1164.ALL;
3
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
4
5
ENTITY LCD_Main IS 
6
  PORT ( clk : IN std_logic;
7
      iRST_N : IN std_logic;
8
          SW : IN std_logic_vector(17 downto 0);
9
       reset : IN std_logic;
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      switch : IN std_logic;
11
     switch2 : IN std_logic;
12
     
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    LCD_DATA : OUT std_logic_vector(7 downto 0);
14
      LCD_RW : OUT std_logic;
15
      LCD_ON : OUT std_logic;
16
    LCD_BLON : OUT std_logic;
17
      LCD_RS : OUT std_logic;
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      LCD_EN : OUT std_logic:='0' 
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       );
20
END LCD_Main;
21
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ARCHITECTURE LCDBody of LCD_Main is
23
  
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  CONSTANT LCD_INITIAL:std_logic_vector(7 downto 0):="00000000";
25
  CONSTANT LCD_LINE1:std_logic_vector(7 downto 0):= "00000100";
26
  CONSTANT LCD_CH_LINE:std_logic_vector(7 downto 0):=LCD_LINE1+16;
27
  CONSTANT LCD_LINE2:std_logic_vector(7 downto 0):=LCD_LINE1+16+1;
28
  CONSTANT LUT_SIZE:std_logic_vector(7 downto 0):=(LCD_LINE2+50)+1;
29
  
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  SIGNAL LUT_DATA:std_logic_vector (11 downto 0):=x"000";--In hex    
31
--  SIGNAL count2 : integer range 0 to 65535 := 0;
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  SIGNAL LUT_INDEX:std_logic_vector(7 downto 0):="00000000";
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  SIGNAL mLCD_DONE:std_logic:='0';
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 -- SIGNAL mLCD_ST:std_logic_vector(5 downto 0):="000000";
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  SIGNAL mLCD_ST:std_logic_vector(1 downto 0):="00";
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  SIGNAL mDLY:std_logic_vector(27 downto 0):=x"0000000";--In hex
37
  SIGNAL mLCD_Start:std_logic:='0';
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  SIGNAL mLCD_DATA:std_logic_vector(7 downto 0):="00000000";
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  SIGNAL mLCD_RS:std_logic:='0';
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  SIGNAL sclk:std_logic:='0';
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  SIGNAL startcount : integer range 0 to 1:=0;
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  SIGNAL D1,D2,D3,D4,D5,D6 : std_logic_vector (11 downto 0):=x"130";
43
44
  COMPONENT LCD_controller IS
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       PORT( iCLK,iRS,iRST_N,istart : IN std_logic;
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                              iDATA : IN std_logic_vector(7 downto 0);
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                              oDone : OUT std_logic;
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                           LCD_DATA : OUT std_logic_vector(7 downto 0);
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                             LCD_RW : OUT std_logic;
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                             LCD_RS : OUT std_logic;
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                             LCD_EN : OUT std_logic
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           );
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  END COMPONENT LCD_controller;
54
  
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  COMPONENT clk_div IS
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         PORT ( iCLK: IN std_logic;
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                sclk: OUT std_logic
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               );
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  END COMPONENT clk_div; 
60
  
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  BEGIN      
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       U0:LCD_controller 
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       PORT MAP(
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                  iCLK => clk,
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                   iRS => mLCD_RS,
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                iRST_N => iRST_N,
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                istart => mLCD_START,
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                 iDATA => mLCD_DATA,
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                 oDone => mLCD_DONE,
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              LCD_DATA => LCD_DATA,
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                LCD_RW => LCD_RW,
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                LCD_RS => LCD_RS,
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                LCD_EN => LCD_EN
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                );
75
                
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        U1:clk_div 
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        PORT MAP( iCLK => clk,
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                  sclk => sclk
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                 ); 
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    LCD_ON <= '1';
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    LCD_BLON <= '1';
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always : process(clk)
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    Begin
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      IF(switch2 = '1' AND switch2'event) THEN
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      startcount <= startcount + 1;
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      END IF;
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         IF(startcount = 1) THEN
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      If(sclk = '1' and sclk'event)THEN
93
      
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----------LCD Line 1--------------
95
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        IF(reset = '0')THEN
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          LUT_INDEX <= "00000000";
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          --mLCD_ST <= "000000";
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          mLCD_ST <= "00";
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          --mDLY <= x"0000000";
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          mLCD_DATA <= "00000000";
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          mLCD_START <= '0';
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          mLCD_RS <= '0';
104
          
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          startcount <= 0;
106
          D1 <= x"130";
107
          D2 <= x"130";
108
          D3 <= x"130";
109
          D4 <= x"130";
110
          D5 <= x"130";
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          D6 <= x"130";
112
          
113
        ELSIF(rising_edge(clk))THEN
114
          IF(LUT_INDEX < LUT_SIZE)THEN
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            case mLCD_ST is
116
              when "00" => mLCD_DATA <= LUT_DATA(7 downto 0);
117
                          mLCD_RS   <= LUT_DATA(8);
118
                          mLCD_START<= '1';
119
                          mLCD_ST   <= "01";
120
              
121
              when "01" => IF(mLCD_DONE = '1') THEN
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                          mLCD_START <= '0';
123
                          mLCD_ST    <= "10";
124
                       END IF;
125
                          
126
              when "10" => IF(switch = '1')THEN
127
                        IF(LUT_DATA = x"080")THEN
128
                          mLCD_ST <= "11";
129
                        END IF;
130
                       END IF; 
131
                            
132
               when "11" => LUT_INDEX <= LUT_INDEX + 1;
133
                       mLCD_ST   <= "00";
134
            end case;
135
          ELSE
136
            IF(sclk = '1')THEN
137
              LUT_INDEX <= LCD_INITIAL;
138
            END IF;
139
          END IF;
140
        END IF;
141
      END IF;
142
      END IF;
143
END PROCESS always;    
144
145
146
147
----READING OF LCD COMMAND----
148
check:process(LUT_INDEX)
149
      begin
150
151
  case LUT_INDEX is  
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   when LCD_INITIAL+0=>LUT_DATA<=(x"030");
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   when LCD_INITIAL+1=>LUT_DATA<=(x"00C");         
154
 --  when LCD_INITIAL+2=>LUT_DATA<=(x"001");          
155
   when LCD_INITIAL+2=>LUT_DATA<=(x"006");           
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   when LCD_INITIAL+3=>LUT_DATA<=(x"080");
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158
   
159
160
   
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   when LCD_LINE1 + 1 => LUT_DATA<=(x"130");
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   when LCD_LINE1 + 2 => LUT_DATA<=(x"130");
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   when LCD_LINE1 + 3 => LUT_DATA<=(x"130");
164
   when LCD_LINE1 + 4 => LUT_DATA<=(D6);
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   when LCD_LINE1 + 5 => LUT_DATA<=(D5);
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   when LCD_LINE1 + 6 => LUT_DATA<=(x"13a");
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   when LCD_LINE1 + 7 => LUT_DATA<=(D4);
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   when LCD_LINE1 + 8 => LUT_DATA<=(D3);
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   when LCD_LINE1 + 9 => LUT_DATA<=(x"13a");
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   when LCD_LINE1 + 10=> LUT_DATA<=(D2);
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   when LCD_LINE1 + 11=> LUT_DATA<=(D1);
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--   when LCD_LINE1 + 12=> LUT_DATA<=(x"130");
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--   when LCD_LINE1 + 13=> LUT_DATA<=(x"130");
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--   when LCD_LINE1 + 14=> LUT_DATA<=(x"130");
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--   when LCD_LINE1 + 15=> LUT_DATA<=(x"130");
176
--   when LCD_LINE1 + 16=> LUT_DATA<=(x"130");  
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   when others => LUT_DATA <= (x"000");
178
179
   end case;   
180
181
  end process check; 
182
end LCDBody;

von P. K. (pek)


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A clocked process has just one active edge and depends on just one 
single clock.

Yours doesn't:

> If(sclk = '1' and sclk'event)THEN
> ...
>   ELSIF(rising_edge(clk))THEN

As there are no registers with dual clock inputs, the tool is not able 
to infer them.

: Edited by User
von Lothar M. (lkmiller) (Moderator)


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Afkar O. wrote:
> always : process(clk)
Additionally the simulation result is incorrect due to the incomplete 
sensitivity list.

>  IF(switch2 = '1' AND switch2'event) THEN
>    startcount <= startcount + 1;
>  END IF;
A bouncing asynchronous input signal never ever must be used this way. 
Instead synchronize the switch to the one and only "clk" and then add an 
edge detection to that synchronized signal.

For simplicity a beginners design MUST have only one clock. All actions 
in the design have to be synchronous to that one "clk". All the rest is 
done by clock enable signals.

See how ALL the other designs are made. They all look like this:
1
  process (reset, clock)
2
  begin
3
    if reset = '1' then
4
      -- set the reset conditions
5
    elsif rising_edge(clk)
6
      -- do what has to be done
7
      if startcount = 1 then 
8
        -- here startcount=1 is a clock enable
9
      end if;
10
    end if
11
  end process;
If your design has another structure its wrong in >>99% of all possible 
cases.

And the structure of your design is absolutely strange like this:
1
  always : process(clk)
2
  Begin
3
    IF(switch2 = '1' AND switch2'event) THEN  -- this is a clock!
4
      .... 
5
    END IF;
6
      
7
    IF(startcount = 1) THEN -- this is a clock enable outside a clocked block
8
      If(sclk = '1' and sclk'event)THEN
9
        IF(reset = '0')THEN
10
          -- some kind of synchronous reset          
11
        ELSIF(rising_edge(clk))THEN -- a clock "inside" a clock?
12
          .... 
13
            IF(sclk = '1')THEN -- this here is unnecessary because here sclk MUST be '1' (see the condition 5 lines above)
14
              ...
15
            END IF;
16
          ...
17
        END IF;
18
      END IF;
19
    END IF;
20
  END PROCESS always;
Do you see the difference?

: Edited by Moderator
von Afkar O. (Company: nanyang polytechnic) (afkarsosman)


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Hi Mr. Lothar Miller,

I understand where am i going wrong now. Im going to try and change the 
codes and try again. Thank you for your help! I really appreciate it!

If there are any questions I'll be sure to post it here.

Regards,
Afkar O.

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