Hello there, when trying to synthesize that code i get the following
error from ise
ERROR:Xst:827 - line 18: Signal count cannot be synthesized, bad
synchronous description. The description style you are using to describe
a synchronous element (register, memory, etc.) is not supported in the
current software release.
do you have any idea why that happens ?
here is the code
1 | library ieee;
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2 | use ieee.std_logic_1164.all;
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3 | use ieee.numeric_std.all;
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4 | entity alt_clock is
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5 | generic (time1 : integer:=3);
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6 | port(clk,rst: in std_logic;
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7 |
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8 |
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9 | done: out std_logic);
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10 | end alt_clock;
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11 |
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12 | architecture aarch of alt_clock is
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13 |
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14 |
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15 |
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16 | begin
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17 | P0:process(clk) -- this is the line 18
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18 | variable count :integer range time1 downto 0;
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19 | begin
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20 | if clk'event and clk='1' and rst='1' then
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21 | count:=0;
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22 | done<='0';
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23 | elsif clk'event and clk='1' and rst='0' then
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24 | if count<time1 then
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25 | count:=count+1;
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26 | done<='0';
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27 | elsif count=time1 then
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28 | done<='1';
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29 | count:=0;
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30 | else null;
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31 | end if;
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32 |
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33 | end if;
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34 |
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35 |
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36 |
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37 |
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38 | end process;
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39 |
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40 |
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41 | end aarch;
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