Forum: FPGA, VHDL & Verilog Simple clock counter says it cant be synthesized (vhdl)

von Crim (Guest)

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Hello there, when trying to synthesize that code i get the following 
error from ise
 ERROR:Xst:827 -  line 18: Signal count cannot be synthesized, bad 
synchronous description. The description style you are using to describe 
a synchronous element (register, memory, etc.) is not supported in the 
current software release.

do you have any idea why that happens ?
here is the code
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity alt_clock is
  generic (time1 : integer:=3);
  port(clk,rst: in std_logic;
       done: out std_logic);
end alt_clock;

architecture aarch of alt_clock is

P0:process(clk) -- this is the line 18
  variable count :integer range time1 downto 0;
    if clk'event and clk='1' and rst='1' then
    elsif clk'event and clk='1' and rst='0' then
      if count<time1 then
      elsif count=time1 then
      else null;
      end if;
    end if;

end process;

end aarch;

von Donni D. (donnidonis)

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are you sure you want to have a syncron reset? If so, make one clk'event 
and in there a if rst=x then...
Also every signal which you read in a process should be in the process 
sensitivity list.
And why declare an integer from three to zero? I count numbers ascending

: Edited by User
von Lothar M. (lkmiller) (Moderator)

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Crim wrote:
> Hello there, when trying to synthesize that code i get the following
> error from ise
Have a look in the Synthesizers User Guide. In it you find how you must 
write your VHDL code to get  your desired components.
If you don't find your specific way of description, then the synthesizer 
cannot translate it to hardware.

If your case the problem is the "double clock". This way of description 
you can find nowhere...

BTW: forget variables fir the first weeks doing VHDL. They usually 
behave different than you expect.

: Edited by Moderator
von Crim (Guest)

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Thanks a lot everyone :)


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