Simple clock counter says it cant be synthesized (vhdl)

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity alt_clock is

  generic (time1 : integer:=3);

  port(clk,rst: in std_logic;

       done: out std_logic);

end alt_clock;

architecture aarch of alt_clock is

begin

P0:process(clk) -- this is the line 18

  variable count :integer range time1 downto 0;

  begin 

    if clk'event and clk='1' and rst='1' then

      count:=0;

      done<='0';

    elsif clk'event and clk='1' and rst='0' then

      if count<time1 then

        count:=count+1;

        done<='0';

      elsif count=time1 then

        done<='1';

        count:=0;

      else null;

      end if;

    end if;

end process;

end aarch;