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Forum: FPGA, VHDL & Verilog Matrix creation in VHDL


Author: martin49 (Guest)
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Hello,

I would like to calculate the inverse of a matrix in VHDL.

From matrix creation:
"
library ieee;
use ieee.std_logic_1164.all;

entity test is

end test;

architecture behave of test is
type dataout is array (6 downto 0,11 downto 0) of std_logic;
signal a : dataout := ("000000000000", "000000111111", "101010101010",
                       "010101010100","111111111111","111111000000","111001100110");
signal b : std_logic;
begin  -- behave
  process

  begin  -- process
    for i in 0 to 6 loop
      for j in 0 to 11 loop
        b <= a(i,j);
        wait for 5 ns;
      end loop;  -- j
    end loop;  -- i
    wait;
  end process;

end behave;
"

How can I do ?

Thanks you

Author: Lothar Miller (lkmiller) (Moderator)
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martin49 wrote:
> I would like to calculate the inverse of a matrix in VHDL.
Just for simulation or on real hardware?
If the second: what hardware and what toolchain?

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