St. D. wrote:
> I just do not want to write the reset operations twice...
So, only use a synchronous reset. Why should you use two ways of reset?
What kind of flipflop can handle that?
Simply write it like all others around the world:
if rising_edge(sys_clk_i) then
if srst_i = '1' then
-- Reset operations
-- Normal operation
> However, the synthesis tools (Vivado & Synplify) complain about that
Indeed, there is NO such a flipflop with two clock inputs inside a FPGA.
Read the synthesizers user guide to figure out, whats allowed and how
you must wirte it.
> (they think that srst_i must also be in the sensitivity list)
They do not care a little bit about that incomplete sensitivity list.
They tell you just with a short warning or info, that with an incomplete
the simulation will not match the real hardware. The sensitivity list is
for the simulator ONLY.