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Forum: FPGA, VHDL & Verilog BEL constrain error


Author: Raza (Guest)
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Hello,

      I'm trying to use the BEL constraint but giving me an error.

Constraint
INST "ring_0_and00001" BEL = G;
INST "ring_0_and00001" LOC = "SLICE_X0Y0";

Error
Pack:2811 - Directed packing was unable to obey the user design
   constraints (LOC=SLICE_X0Y0) which requires the combination of the 
symbols
   listed below to be packed into a single component.

Author: Duke Scarring (Guest)
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Raza wrote:
> I'm trying to use the BEL constraint but giving me an error.
That is an declaration. What is the question?

Which vendor, which device and which toolchain do you use?

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