BEL constrain error

Raza Guest #4795852
Rate this post
• ▲ useful
▼ not useful 
Hello,

      I'm trying to use the BEL constraint but giving me an error.

Constraint
INST "ring_0_and00001" BEL = G;
INST "ring_0_and00001" LOC = "SLICE_X0Y0";

Error
Pack:2811 - Directed packing was unable to obey the user design
   constraints (LOC=SLICE_X0Y0) which requires the combination of the 
symbols
   listed below to be packed into a single component.
Reply Quote Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Report post
Watch this topic

Reply

Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.

Formatting
  • [c]C-Code[/c]
  • [vhdl]VHDL-Code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]
  • [[Title]] – link to an article
  • Link to another post: right-click its post ID (#8078628), copy the address, paste it into the text

More about formatting

Post long source code as an attachment, not in the text.

Your name and e-mail address

Already registered? Log in

Not shown to anyone. We send you a link; your post appears once you confirm it there.

By submitting you create a free account and accept the terms of use.