EmbDev.net

Forum: FPGA, VHDL & Verilog BEL constrain error


BEL constrain error
von Raza (Guest)

Rate this post
0 ▲ useful
▼ not useful 
Hello,

      I'm trying to use the BEL constraint but giving me an error.

Constraint
INST "ring_0_and00001" BEL = G;
INST "ring_0_and00001" LOC = "SLICE_X0Y0";

Error
Pack:2811 - Directed packing was unable to obey the user design
   constraints (LOC=SLICE_X0Y0) which requires the combination of the 
symbols
   listed below to be packed into a single component.

Report post Edit Move Thread sperren Anmeldepflicht aktivieren Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote
Re: BEL constrain error
von Duke Scarring (Guest)

Rate this post
0 ▲ useful
▼ not useful 
Raza wrote:
> I'm trying to use the BEL constraint but giving me an error.
That is an declaration. What is the question?

Which vendor, which device and which toolchain do you use?

Report post Edit Delete Quote selected text Reply Reply with quote
Watch this topic | Disable multi-page view

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]



Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.