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Forum: FPGA, VHDL & Verilog Linking Modules Instantiations


Author: Benjamin L. (Guest)
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In my code I have two instantiations of different modules:

module1 myModule1 (in1, out1);
module2 myModule2 (out1, out2);

As you can see, my main goal is to make the input on my second module be 
dependent on the result of the output of my first module. However, to my 
understanding, out1 doesn't have a value at the beginning since 
everything happens at the same time and out1 hasn't been calculated from 
the first module. How am I supposed to go about this in code?

Author: P. K. (pek)
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If you give all storage elements (e.g. registers, memories) an initial 
value and you have all inputs well defined, everything is OK.

If not (i.e. you'll get unknown or undefined signals in your simulation) 
track the signals down to where they origin from and give initial 
values.

Even if you don't give initial values for the storage elements, they 
should eventually end up in defined states in a good design (inputs are 
mandatory to be well-defined, of course).

: Edited by User
Author: Lothar Miller (lkmiller) (Moderator)
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Benjamin L. wrote:
> out1 doesn't have a value at the beginning
Of course it has.
It has a undefined or (if you have been clever) any initialized value...

> out1 hasn't been calculated from the first module.
What kind of "module" ist that? Is it combinatorial or is it registered?

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