I am currently trying to use an nmos and pmos in my verilog code. However, when I try to synthesize my code I get an error that says: "cannot synthesize MOS switch gate primitive". What is the solution to this error?
Benjamin L. wrote: > However, when I try to synthesize my code What platform? What target? What toolchain? For sure you cannot synthesize a simple transistor gate on a FPGA, because all of the transistors in there are used by the manufacturer...
@Benjamin L. (Guest) >"cannot synthesize MOS switch gate primitive". What is the solution to >this error? Just forget about it and learn what verilog is really used for.
So your saying it is impossible to use pmos and nmos declarations when dealing with FPGAs? If so, then why do they even include those type declarations in verilog? Is there any other possible workaround, per say, creating the pmos from scratch?
1) If you really want to synthesize: Read about your FPGA's primitives. They're called primitives because that's the most atomic thing you have access to on your FPGA. 2) If you want to simulate: You could certainly do that, but typically people use Spice or Qucs models for MOS transistor simulation
Benjamin L. wrote: > So your saying it is impossible to use pmos and nmos declarations when > dealing with FPGAs? You got it. > If so, then why do they even include those type declarations in verilog? Who are "they"? The (until now unknwon) FPGA manufacturer? Or who else? > If so, then why do they even include those type declarations in verilog? To keep thing short: out of the 100% that is possible to do with Verilog about 5% can be synthesized on a FPGA. With that transistor You try to do something out of those 95% impossible things... The relevant document for Verilog on a FPGA is the synthesizers manual from the FPGA manufacturer. In that manual you find synthesizable templates and code snippets. > Is there any other possible workaround, per say, creating the pmos from > scratch? As already said: NOT ON A FPGA. If you want "your" own transistor, then you must do "your" own ASIC. Alternatively you can pick one of the parts out of an ASIC manufacturers library... BTW: did you read my 3 questions?
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Edited by Moderator
I meant simulate and NOT synthesize. So knowing that, is it possible to simulate such transistors without getting that error? @Lothar Miller I meant the designers of verilog/quartus. Why would they include the functionality of having pmos(...) if you can't even use it
Benjamin L. wrote: > I meant the designers of verilog/quartus. those are completely different people with totally different aims. You may find a Verilog description of a transistor, but for sure you will not find that transistor in any relationship to Quartus. That's because you can use Verilog (in however way) to design that transistor, but Quartus never ever will synthesize it on a Altera/Intel FPGA. To keep things short: Verilog is not Quartus. And Quartus is not Verilog. They overlap just for 5%. Quartus not even is a simulator. It's ModelSim that's used for that job. So at first you must get a clear picture about your toolchain. Otherwise it may be the same like taking a wrecking bar and try to hammer a screw into the wall: wrong tool and wrong strategy for that job..
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