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FPGA vs ASIC - CDC
von Fpga R. (fpga_rookie)

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Hi all,

Is handling CDC issues on FPGA should be (is) any different from 
handling CDC issues on ASIC? I.e., Are the same techniques in ASIC apply 
in FPGA?


Thanks!

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Re: FPGA vs ASIC - CDC
von Gustl B. (-gb-)

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I don't know how it is done in ASICs but i can't think oft any reason 
why there should be any difference.

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Re: FPGA vs ASIC - CDC
von Sym (Guest)

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Basically the same. On some ASIC technologies a special type of 
registers is used for CDC flip-flops. The intension is to have registers 
with better metastability properties to improves the MTBF.
As many ASIC designs use clock gating very extensively, particular care 
has be taken for this aspect as well.

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Re: FPGA vs ASIC - CDC
von Fpga R. (fpga_rookie)

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Sym wrote:
> Basically the same. On some ASIC technologies a special type of
> registers is used for CDC flip-flops. The intension is to have registers
> with better metastability properties to improves the MTBF.
> As many ASIC designs use clock gating very extensively, particular care
> has be taken for this aspect as well.

Thank you for the quick response.

1. Are there special FPGA registers (with better metastability 
properties) designated for CDC?
2. Can you please elaborate on your last statement?
> As many ASIC designs use clock gating very extensively, particular care
> has be taken for this aspect as well

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Re: FPGA vs ASIC - CDC
von Fpga R. (fpga_rookie)

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Also, any other opinions/comments?

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Re: FPGA vs ASIC - CDC
von Sym (Guest)

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> 1. Are there special FPGA registers (with better metastability
properties) designated for CDC?
As far as I know, no. At least not with Xilinx, Altera, Microsemi, 
Lattice. However, you can tell the tools to treat CDC registers 
differently in a sense, to avoid register duplication/merge, pipelining 
and retiming on the first 2/3 registers of the synchronizer. This way 
the MTBF improves.

> 2. Can you please elaborate on your last statement?
Clock gating disables clocks for power saving - a very common feature in 
today's SoC designs. When disabling clocks, synchronization of handshake 
signals or gray pointers may take longer (due to disabled clocks) and 
need to be taken into consideration. That's not different as for an 
FPGA, yet clock gating on an FPGA is less common.

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