Hi there I just did some projects about image processing used VHDL. But i don't know about there code. Could u help me pls? thanks
Ho O. wrote: > Could u help me pls? Not with the information you provided. A first hint for some useful information: What specific problem with what VHDL code on what hardware with what toolchain do you have? What do you ecpext and what do you get instead?
I do not know what to use algorithms to compress images using VHDL code. Could you show me some way?
A tip: Start by looking at JPEG compression C code. Then try to translate the core DCT into HDL (yes, without using HLS!). Likewise, you can also look at various RLE (run length encoding) or huffman coding in principle (you'll need that for the JPEG at a later stage). Reserve at least half a year to hack yourself into the matter. Then come back with questions.
Please visit my tutorial here: fpga4student.blogspot.com I can help you on some DSP projects.
http://www.fpga4student.com/ FPGA digital design projects using Verilog/ VHDL Getting various free FPGA projects and Verilog/ VHDL source code, offering services for any urgent Assignment/ Projects You might like this: Verilog code for a Carry Look Ahead Multiplier Verilog HDL implementation of a Micro-controller (similar to MICROCHIP PIC12) (Part 1) Verilog IMPLEMENTATION OF A MICROCONTROLLER (SIMILAR TO MICROCHIP PIC12) (Part-2- Architecture design) Verilog code for a microcontroller (Part-3) 16-bit Processor CPU design and implementation in LogiSim A multi-cycle 32-bit divider on FPGA using Verilog HDL Image processing on FPGA using Verilog HDL Programmable N-bit switch tail ring counter (VHDL behavior and structural code with testbench) Verilog code for 4x4 Multiplier using two-phase self-clocking system VHDL code for digital clock on FPGA Verilog code for a parking system using Finite State Machine (FSM) Verilog code for Traffic light controller Verilog code for Alarm clock on FPGA VHDL code for the 8-bit Comparator Matrix Multiplication Design using VHDL and Xilinx Core Generator Two ways to load a text file into FPGA or the initial values to a memory in Verilog/ VHDL (synthesizable) Plate License Recognition Verilog/Matlab Implementation on FPGA Xilinx Spartan-6