Hi all, I am working on FPGA and I am using chipscope to verify my designs. In this case I will set the input test patterns and I will verify the corresponding output. But the problem with this method is that, it is time consuming. So, I am searching for techniques to automate the verification in FPGA. Can you please tell me the options available to automate the verification and their pros and cons. Thanks
Deepika A. wrote: > Can you please tell me the options available > to automate the verification and their pros and cons. Nivce try, but isn't that YOUR homework?
Deepika A. wrote: > So, I am searching for techniques to automate the verification in FPGA. Instead of comparing the chipscope results outside, you can do that directly inside the FPGA having two different possibilities: - Assertion based simulation (not synthesizable, but helps find errors already during simulation) - BIST (built-in self test). You gather the data as before, instead of storing in RAM and read to the PC, you have your comparing engine directly within the FPGA. The BIST will tell you go/no-go and even may come up with some diagnostics, if you do it well...
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Hi, if Co-Simulation is not an option, meaning, you are forced to use HW, you might be better off hacking your own chipscope with the more or less well documented features of the JTAG primitives (which are a pain on some older Xilinx-FPGAs). However, having a proper JTAG testing front end (i.e. fast adapter and boundary scan driver routines) can range from a cheap FTDI solution up to a serious investment - depends on how many test vectors you need to play back on your design. Maybe you have to elaborate on what you are targetting at. Cheers, - Strubi