VHDL multiplier block

hi,

a classical one:

Esteban wrote:
> Multiplication: process(x,B)

sensitive list incomplete

This seems, I guess, to be an issue regarding the verification process.

How exactly did you do it? How long was the simulation? How long was it 
in relation to the time, the multiplier takes? How long keeps R the 
uninitialized state?

The main point is, that you possibly forgot, that you describe 
structures rather than writing programs. While the multiplication is 
done, the second line, assigning (or better say transportation) of s32_R 
to R is at and during the very same time in effect, - or say: parallel 
to -, the multiplication.

So, if you stop simulation when the multiplication is done, the transfer 
to R had just begun, not finished, as you may assume.

Whether that assumption matters, depends in turn on whether you 
simulated a real design or not. It is, additionally, true, that such a 
simple "put-through" or say "and identity" in terms of math, is 
optimized away in a synthesized design.

So I assume, that you showed us a simplified process, whose real 
version, make use of the intermediate result s32_R, so that it wasn't 
optimized away, and shows that "delayed" behavior, which you don't 
recognize because you stopped the simulation too early.

Esteban wrote:

1

--Multiplication: process(x,B)

2

--  begin

3

    s32_R <= std_logic_vector(signed(x)*signed(B));

4

    R <= s32_R(15 downto 0);

5

--  end process Multiplication;

Instead of adding s32_R to the sensitivity list I suggest to use a 
variable.
---
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Multiplier is
  port(
  x,B: in std_logic_vector(15 downto 0);
  R: out std_logic_vector(15 downto 0)
  );
end Multiplier;

architecture Behavioral of Multiplier is
begin
  Multiplication: process(x,B)
    variable s32_R: std_logic_vector(31 downto 0);
  begin
    s32_R := std_logic_vector(signed(x)*signed(B));
    R <= s32_R(15 downto 0);
  end process Multiplication;
end Behavioral;
---

You can see a project over multiplication of matrixs here using VHDL:
http://fpga4student.blogspot.sg/2016/11/matrix-multiplier-core-design.html?spref=fb&m=1