# Forum: FPGA, VHDL & Verilog Help with Direct Manipulation of Logic Cells

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Hello, and thanks in advance for any replies.

I am very new to FPGAs and know nothing about how to use HDLs, so
forgive me if none of this makes sense or I have some fundamental
misunderstanding, and any corrections will be very much appreciated.

First I think it will help for me to say what I think I know, so it will
be easier to see where I am coming from. I know that FPGAs are at the
most basic level made of logic cells, and that you can connect them
however you want to do a specific task, and that this is done through
something like VHDL or Verilog.

What I want to be able to do is to connect logic cells directly on a
if there were four logic cells in a grid and you could assign each a
number 1-4, would I be able to (with the help of an HDL), say that cell
1 is connected to cells 2 and 4 and that cell 2 is conncected only to
cell 1, etc.

Any help with this would be greatly appreciated, and if further
clarification is needed I would be more than happy to.

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Garrett S. wrote:
> What I want to be able to do is to connect logic cells directly on a
> very basic level.
Why?

> One way I have been thinking about...
Get the manuals and datasheets of really existing FPGAs and read, how
the designer did that. After a very short time you will see, that there
are a big bunch of parameters within a logic cell you cannot manipulate
that easy way.

> I am very new to FPGAs and know nothing about how to use HDLs
Change that.

> so forgive me if none of this makes sense or I have some fundamental
> misunderstanding
The most significant flaw in your thinking is that you underestimate the
complexity of such a logic cell by several powers of 10. If you could
draw a "wire" inside the FPGA and connect 2 of those logic cells, you
will miss the track after 5 or 10 such connectins. Just because all of
them look the same, but behave entirely differet according to their
init values.

For me the most basic elements of an FPGA are Flipflops and LUTs.
Thats all.
But never ever I will try to connect them on my own. I do it the other
way: I draw a schematic (at least in mind), then I "describe" that
schemtic with VHDL, then I have a look on the generated RTL schematic
and compare it with the one I started. If they match, then my HDL
description is right and the synthesizer will generate the connnection
between the logic cells and initialize the LUTs inside the logic cells
in a way that I wanted.

: Edited by Moderator

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Hi Garrett,

what you're addressing is referred to as a 'net list'. This is a
description similar to the output of a PCB schematic editor, defining
connections between chip pins. On an FPGA you just have primitives
So if you wanted to connect logic on that level, you could do that by
trying to write net lists for it (some tools can take EDIF netlists),
but that is a lot of pain, like trying to write code in hex instead of
assembly.
Moreover, no one would/could support you there, plus not all FPGA
vendors
fully document their primitives on the very physical level, you will
have to reverse engineer quite a bit.
If you wanted to dive in on such a low level, I would recommend to check
the open source approach to the ICE40 FPGAs (former SiliconBlue, now
Lattice).

The way more maintainable and pretty established approach is to describe
the logic primitives in HDL. You can go for a coding style that is very
primitive-focused, there are also options to connect these primitives
graphically. However, you'll be facing similar obstacles in
maintainability as with other graphical programming solutions. This is a
popular discussion topic, IMHO, the language always wins for a robust
long term solution.

Greetings,

- Strubi

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Thanks for the replies,

Lothar M. wrote:
> The most significant flaw in your thinking is that you underestimate the
> complexity of such a logic cell by several powers of 10. If you could
> draw a "wire" inside the FPGA and connect 2 of those logic cells, you
> will miss the track after 5 or 10 such connectins. Just because all of
> them look the same, but behave entirely differet according to their
> init values.
>
> For me the most basic elements of an FPGA are Flipflops and LUTs.
> Thats all.
> But never ever I will try to connect them on my own. I do it the other
> way: I draw a schematic (at least in mind), then I "describe" that
> schemtic with VHDL, then I have a look on the generated RTL schematic
> and compare it with the one I started. If they match, then my HDL
> description is right and the synthesizer will generate the connnection
> between the logic cells and initialize the LUTs inside the logic cells
> in a way that I wanted.
The application that I have in mind is using a genetic algorithm to
design circuits, and in order to do this I have to be able to manipulate
the smallest part of the FPGA that has reconfigurable connections. What
im wondering is, with my application would I need to manipulate those
internal parameters? Or even better, could I also manipulate these
smaller parameters just like I want to manipulate the larger logic cell?

Strubi wrote:
> The way more maintainable and pretty established approach is to describe
> the logic primitives in HDL. You can go for a coding style that is very
> primitive-focused, there are also options to connect these primitives
> graphically. However, you'll be facing similar obstacles in
> maintainability as with other graphical programming solutions. This is a
> popular discussion topic, IMHO, the language always wins for a robust
> long term solution.
Knowing that I won't actually be designing the circuits myself, rather a
genetic algorithm will be doing all the heavy lifting, it seems like
using an HDL is definitely my best bet. But any further insight will
definitely be appreciated.

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Garrett S. wrote:
> The application that I have in mind is using a genetic algorithm to
> design circuits
Do you mean a generic algorithm?

> and in order to do this I have to be able to manipulate
> the smallest part of the FPGA that has reconfigurable connections.
You must talk to the designer of the FPGA. He is the only one that knows
about the depp internal structure. You will not get this confident
information just around the corner...

> Or even better, could I also manipulate these
> smaller parameters just like I want to manipulate the larger logic cell?
I hope you have some years of time for that. Xilinx is working the last
10 years on (partial) reconfiguration at runtime. Maybe you should get
in touch with them.

> What im wondering is, with my application would I need to manipulate
> those internal parameters?
I don't think that makes sense. Because you will have to adapt your
algorithm with the slightest internal change of a FPGA. Even with
minuscle variations you must check your whole application. And then you
can forget about switching over to a newer technologie or to another
FPGA supplier.

The usual and the best way is to stay on RTL-level with combinatorial
gates and flipflops and let do the FPGA supplier the rest...

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Hi,

you'll be having a very hard time to fit genetic algorithms into FPGA
logic whose makers will not tell you exactly how it works.
There might be a chance with the approach I mentioned, but that is still
years behind a dynamic reconfiguration, I believe.
There are some experiments on some FPGA that allows to manipulate the
SRAM cells from within, but that also will take months to get somewhere,
outcome totally unsure, because it's all undocumented.

The more pragmatic approach would be to develop the framework for the
genetic algo in HDL.
There are some ideas around in the industry to use FPGAs for optimized
string searches, like for DNA sequence analysis or special pattern
matching for enzyme structures. Are you heading that way?
You might be better off designing a very simple CPU core for that
purpose and use microcode to actually implement the switches between the
logic that should be turned into a "genetic algorithm". Stack machines
do a good job there, but could be a pain to program, if you want them to
be compact AND fast. But if you have the money to invest into such a
novel approach, you could afford big buck silicon and instance like
50-100 of those cores.
Question is, if you can't do the job with a GPU instead. Most people go
for that, eventually.
Very interesting topic, but it will need some breakthrough to become
feasible in the next 2-3 years, I believe.

Cheers,

- Strubi

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You can do this with the "fpgaeditor" tool in the "old" xilinx tools
(ISE).

https://vjordan.info/log/fpga/spartan6-slice-m-configuration.html

Best regards,

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I think he needn't know the exact hardware details. Threre is a nice
paper at http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.50.9691
. The author does not use reconfiguration but generates bitstreams on a
computer.

The idea is to implement evolution. Take one bitstream as a block-box,
then look if the device soed what it should do and if not go to the next
generation, generate a new bitstream from the old bitstream but with
some bits changed at random. And you need a test for fitness or if the
current configuration does what it should and if it is better than a
generation before.
This looks doable ob the FPGA itself, some static logic generates for
partial reconfiguration and another static logic evaluates the current
configuration.

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